A sensor apparatus includes a photosensitive sensor, a cover, and a moving mechanism. The photosensitive sensor includes a first lens and a second lens which focus on a photosensitive element. The cover includes a first slit arranged on an optical axis of the first lens and a second slit arranged on an optical axis of the second lens. The moving mechanism is configured to move the photosensitive sensor and the cover relative to each other so that the second slit is arranged on the optical axis of the first lens.

A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.

An electronic device capable of placing restrictions on processor usage is disclosed. The electronic device may include: a memory; and a processor including a first core and a second core. The memory may store instructions that, when executed by the processor, cause the first core to transition from an active state to an idle state in response to a restriction signal for the first core, and cause the first core to transition to a power save state when the first core remains in the idle state for at least a preset time. For hot-unplugging, as the electronic device does not transition a core to an offline state, it does not have to perform cleanup operation on the memory and variables. Hence, it is possible to reduce the latency time due to hot-unplugging.

The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.

According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.

According to various embodiments of the present disclosure, an electronic device includes: a housing; a touch circuit including a plurality of TX electrodes, and a plurality of RX electrodes arranged to cross over the plurality of TX electrode; a flexible display which includes the touch circuit, and which can be withdrawn from the inner space of the housing; a touch controller; and a processor operatively connected to the touch circuit, the flexible display and the touch controller, wherein the touch controller applies a driving signal by using the plurality of TX electrodes of the touch circuit, acquires the driving signal by using the plurality of RX electrodes, confirms a capacitance value on the basis of the acquired driving signal, and confirms information about a folded area of the flexible display on the basis of the capacitance value, and the processor can set an activation area for an unfolded area of the flexible display on the basis of the folded area of the flexible display. Various embodiments, in addition to various embodiments disclosed in the present document, are also possible.

A method of peak power management (PPM) is provided for two NAND memory dies. each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

Provided are electronic devices and methods for power reduction in systems with multiple memory ranks. The electronic device includes a memory system including first and second memory ranks and a memory controller connected to the memory system and configured to control power of the memory system. The memory controller being configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank.