A memory system includes a memory medium and a memory controller configured to control the memory medium. The memory controller includes a training core and a training block. The training core is configured to detect a delay time of a clock signal to generate a delay selection signal during a training operation for the memory medium. The training block is configured to generate a delayed clock signal which is delayed by a time period set according to the delay selection signal outputted from the training core.

A controller of a memory sub-system can, responsive to providing a command completion signal to a host, mark a portion of a plurality of commands that are addressed to a same logical block of the memory devices, reorder the marked portion of the plurality of commands, wherein write commands from the marked portion of the plurality of commands are given priority over read commands from the marked portion of the plurality of commands, execute a newest write command from the marked portion of the plurality of commands prior to executing read commands, addressed to the same logical block, from the marked portion of the plurality of commands, and execute read commands from the marked portion of the plurality of commands in on an order in which the read commands were received and after the execution of the newest write command, wherein the read commands are executed responsive to an execution of the newest write command.

A processing-in-memory (PIM) device includes a memory circuit, a processing circuit configured to receive arithmetic data from the memory circuit to perform an arithmetic operation, an information storage configured to store arithmetic operation information that defines the arithmetic operation, a processing control circuit configured to generate a first arithmetic control signal and a second arithmetic control signal based on the arithmetic operation information from the information storage and an internal initiation command, and a memory control circuit configured to generate a memory control signal based on the second arithmetic control signal and configured to transmit the memory control signal to the memory circuit.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

In one aspect of metadata track entry sorting in accordance with the present description, recovery logic sorts a list of metadata entries as a function of a source data track identification of each metadata entry to provide a second, sorted list of metadata entries, and generates a recovery volume which includes data tracks which are a function of one or more data target tracks identified by the sorted list of metadata entries. Because the metadata entry contents of the sorted list have been sorted as a function of source track identification number, the particular time version of a particular source track may be identified more quickly and more efficiently. As a result, recovery from data loss may be achieved more quickly and more efficiently thereby providing a significant improvement in computer technology. Other features and aspects may be realized, depending upon the particular application.

A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

A storage device includes: a memory device including a plurality of memory blocks organized into a plurality of zones; and a memory controller configured to perform a write operation on the plurality of zones. The memory controller is operable to divide at least one zone among the plurality of zones into subzones when the memory controller receives data corresponding to consecutive logical addresses provided from a host, and control the memory device to store the data in at least one subzone among the subzones. The at least one zone can be divided based on a characteristic of the memory device and a size of the data.

Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

A method and an apparatus for upgrading a SSD firmware compatible with an RAID and a non-RAID is provided. The method includes: packing two firmware versions including an RAID firmware and a non-RAID firmware together, when the two firmware versions need to be released; adding a configuration information with a fixed length of bytes to a firmware header of a resulting packed firmware, where the configuration information includes: index values, offsets, and file sizes of the RAID firmware and the non-RAID firmware; determining, according to an internal information of an SSD, whether a matching firmware version thereof is the RAID firmware or the non-RAID firmware; and comparing the internal information of the SSD with the configuration information of the firmware header, selecting a matching index value, and reading a corresponding firmware according to the offset and the file size.

Tuning information associated with a storage device of a plurality of storage devices is received. One or more characteristics associated with the storage device are determined. The tuning information and the one or more characteristics are provided to the plurality of storage devices, wherein providing the tuning information causes a set of the plurality of storage devices to apply the tuning information based on the one or more characteristics.