Methods, apparatus, systems and articles of manufacture are disclosed to utilize non-volatile memory for computer system boot. An example processor platform includes a non-volatile memory coupled to a processing unit via a bus, and a microcontroller to: configure the processing unit to store, on the non-volatile memory, a heap and a stack for execution of boot code, and configure the processing unit to execute the boot code stored on the non-volatile memory.

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for reading data with an optimization read voltage (RV) table. The method includes: determining one set of RVs for a designated memory-cell type according to a current environmental parameter of a NAND-flash module and content of the optimization RV table; and reading data on a page corresponding to the designated memory-cell type from the NAND-flash module with the set of RVs. The optimization RV table includes multiple records and each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

Systems and methods are disclosed that are of retrieving, by a processing device, a codeword stored at a memory sub-system, determining parity data of the codeword, generating additional parity bits based on one or more bits of the parity data of the codeword, and generating host data by decoding the codeword using the additional parity bits.

A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.

Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

A memory system includes a nonvolatile memory and a controller that includes an encoder configured to encode a first group of data including a plurality of first data, each first data having a plurality of bits. The encoder is configured to perform a first encoding process of generating a second group of data including a plurality of second data from the plurality of first data in the first group, and a second encoding process of generating a third group of data including a plurality of third data from the plurality of second data in the second group. A logical value of “1” is less likely to be the value in an n-th bit position of the plurality of third data in the third group than the value in any of the bit positions of the plurality of second data in the second group.

A storage device includes a nonvolatile memory device; and a controller configured to, sequentially receive first read commands and a first write command, the first write command being associated with first write data, slice the first write command to generate a plurality of sub-commands, slice the first write data to generate a plurality of sub-data elements, and alternately transmit, to the nonvolatile memory device, at least one read command of the first read commands, and one sub-command of the plurality of sub-commands and one sub-data element of the plurality of sub-data elements.

An illustrative embodiment disclosed herein is an apparatus including a processor and a memory. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a first object and a second object in a first region based on the first object and the second object having a first policy. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a third object in a second region based on the third object having a second policy. In some embodiments, a virtual disk includes the first region and the second region.