Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

Embodiments of the present disclosure provide a DRAM-based storage caching method for a smart terminal, and the method includes: capturing an IO delivered by an upper-layer application; determining, based on a configuration policy, whether the IO belongs to a pre-specified to-be-cached IO type; and when the IO belongs to the pre-specified to-be-cached IO type, performing a corresponding caching operation for the IO in a DRAM disk based on a read/write type of the IO and a preset caching policy, where the DRAM disk is a block device created by using a reserved part of DRAM space of an operating system.

An information processing apparatus includes a nonvolatile memory, a count processing portion, and an execution processing portion. The count processing portion is configured to count, for each cycle of a specific time period, a write count that is a number of times data has been written to the nonvolatile memory. The execution processing portion is configured to execute a specific process when the write count that is counted during the specific time period by the count processing portion reaches a specific count.

The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Apparatuses, systems, and techniques to transform and store information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed and stored.

Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more GPU caches.

Apparatuses, systems, and techniques to indicate storage locations of information to be mapped from a first tensor to a second tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate one or more storage locations of information to be mapped from a first tensor to a second tensor.

Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.

Apparatuses, systems, and techniques to generate a tensor mapping. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a mapping from a first tensor to a second tensor to be generated.

Apparatuses, systems, and techniques to store information in a plurality of storage locations allocated to a graphics processing unit (GPU). In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored in a plurality of storage locations allocated to a first GPU.