Data transformation caching in an artificial intelligence infrastructure that includes one or more storage systems and one or more graphical processing unit (GPU) servers, including: identifying, in dependence upon one or more machine learning models to be executed on the GPU servers, one or more transformations to apply to a dataset; generating, in dependence upon the one or more transformations, a transformed dataset; storing, within one or more of the storage systems, the transformed dataset; receiving a plurality of requests to transmit the transformed dataset to one or more of the GPU servers; and responsive to each request, transmitting, from the one or more storage systems to the one or more GPU servers without re-performing the one or more transformations on the dataset, the transformed dataset.

A method includes storing a data group in a first zone of a plurality of radial zones of a data storage disc. Each different one of the plurality of zones has a different throughput level. The method further includes obtaining information related to an access frequency of the data group stored in the first zone of the plurality of zones. Based on the information related to the access frequency of the data group and the different throughput levels of the different zones, a determination is made as to whether to migrate the data group from the first zone of the plurality of zones to a second zone of the plurality of zones.

A method is used in managing migration of virtual file servers. The method migrates a virtual file server from a source storage processor to a destination storage processor in a storage system. The storage system includes the source and the destination storage processors. The virtual file server comprises a root file system, a configuration file system, and a set of user file systems. The method enables concurrent access to the root file system from both source and destination storage processors during the migration until the set of user file systems is migrated from the source storage processor to the destination storage processor.

Techniques are described for performing data storage optimization. A first I/O workload for a first data portion of a first snapshot of a first logical device is tracked. First processing is performed by a data storage optimizer to determine a set of one or more data movement optimizations. The first processing uses the first I/O workload for the first snapshot. The set of one or more data movement optimizations include a first data movement that is any of a promotion to move data included in the first data portion from a first storage tier to a higher performance storage tier and a demotion to move data included in the first data portion from the first storage tier to a lower performance storage tier. The first data movement is performed.

Example implementations relate to a storage memory direct access (SMDA) provider. The SMDA provider may pin a storage memory region to a memory address of a consumer machine, the storage memory region corresponding to a storage range of a storage device requested by the consumer machine. The SMDA provider may atomically commit data in the storage memory region accessed by the consumer machine via the memory address.

A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.

To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing command is executed. A transfer unit transfers the writing data from the first memory to a second memory at a predetermined timing. A reading unit performs reading of reading data from the second memory with higher priority than from the first memory when a reading command is executed.

In accordance with embodiments of the present disclosure, an information handling system may include a processor, a memory communicatively coupled to the processor, and an allocation agent embodied in a program of executable instructions and configured to, when executed by the processor, maintain an attribute index setting forth one or more attributes for each of one or more memory modules of the memory, and based on the one or more attributes and one or more memory requirements of an application executing on the information handling system, dynamically allocate the one or more memory modules to a namespace associated with the application.

A write frequency of a non-volatile memory is determined at a fine granularity while suppressing consumption of the volatile memory. When it is determined that a copy of specified data from a specified physical storage area to another physical storage area is to be executed, a controller reads the specified data and specified write frequency information, selects a write destination physical storage area group from a plurality of physical storage area groups based on the specified write frequency information and classification information, selects a write destination physical storage area from the write destination physical storage area group, changes the specified write frequency information, writes the specified data to the write destination physical storage area, writes the changed specified write frequency information to the non-volatile memory, and updates translation information based on the write destination physical storage area group and the write destination physical storage area.

Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.