Patent classifications
G06F3/0646
Apparatus and method for accelerating operations in a processor which uses shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
DATA VOLUME MANAGER
A system comprises one or more computer hosts each comprising one or more Central Processing Units, one or more file systems, a host operating system, and one or more memory locations, wherein said CPUs are operatively connected to said one or more memory locations and configured to perform one or more of: execute one or more software on a host OS, wherein said software is configured to create one or more snapshots of said one or more file systems, identify one of said snapshots as an originator snapshot, identify a second snapshot, determine differences between said second snapshot and said originator snapshot, determine one or more file system calls transforming said originator snapshot into said second snapshot based on said differences and store said one or more file system calls that transform said originator snapshot into said second snapshot in one or more of non-transitory storage and transitory storage.
Aggregated background processing in a data storage system to improve system resource utilization
Techniques for aggregating background processing in a data storage system. Blocks are identified having contents on which a data operation was not performed in-line. The background data operation is prevented for blocks that will no longer be accessed by the host computer because they are only mapped to files implementing data objects that are scheduled for future deletion. A region of blocks may be selected that meets a criteria for performing a background free space operation, and the background data operation may be performed on the contents of blocks in the selected region while the contents of those blocks are being relocated to other blocks while performing the background free space operation. While performing the background data operation, blocks may be freed from files that implement data objects scheduled for future deletion.
DIRECT DATA MOVE BETWEEN DRAM AND STORAGE ON A MEMORY MODULE
A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.
ACCELERATED LEARNING IN ADAPTIVE REBUILDING BY APPLYING OBSERVATIONS TO OTHER SAMPLES
A method begins by obtaining scoring information for a rebuilding for one or more storage units of a set of storage units of the DSN. The method continues by determining based on the scoring information that a first input/output rate of a plurality of input/output rates for a first rebuilding rate of a plurality of rebuilding rates exceeds a difference threshold compared to an initial first input/output rate for the first rebuilding rate. The method continues by adjusting a plurality of initial input/output rates based on the first input/output rate to produce a plurality of updated input/output rates. The method continues by generating an updated plurality of scores for the plurality of rebuilding rates based on the plurality of updated IO rates and implementing the rebuilding in accordance with the updated plurality of scores.
Systems and methods for taking snapshots in a deduplicated virtual file system
A computer-implemented method for taking snapshots in a deduplicated virtual file system may include (1) maintaining a deduplicated virtual file system that stores, at an original location within a non-virtual file system, at least one configuration file storing metadata for a target file and an extent map for the target file, the extent map defining how to construct the target file from deduplicated data segments in a deduplicated storage system, (2) receiving a request to take a snapshot of the target file corresponding to the configuration file, (3) copying the configuration file storing metadata for the target file and the extent map for the target file into a snapshot location within the non-virtual file system, and (4) transmitting a file reference request to the deduplicated storage system to add a file reference within the deduplicated storage system. Various other methods, systems, and computer-readable media are also disclosed.
METHOD AND APPARATUS FOR STORING INFORMATION USING AN INTELLIGENT BLOCK STORAGE CONTROLLER
Methods, devices, and media for improving data storage reliability and efficiency comprising: creating at least one logical storage drive comprising a plurality of logical blocks; mapping the at least one logical storage drive to at least one physical storage drive based on many-to-one mapping or one-to-many mapping, wherein the at least one physical storage drive comprises a plurality of physical blocks; and applying a compression algorithm to data held in one or more logical blocks, aggregating units of the data, and storing the units of the data into one or more physical blocks.
METHOD AND APPARATUS FOR STORING INFORMATION USING AN INTELLIGENT BLOCK STORAGE CONTROLLER
Methods, devices, and media for improving data storage reliability and efficiency comprising: creating at least one logical storage drive comprising a plurality of logical blocks; mapping the at least one logical storage drive to at least one physical storage drive based on many-to-one mapping or one-to-many mapping, wherein the at least one physical storage drive comprises a plurality of physical blocks; and applying a compression algorithm to data held in one or more logical blocks, aggregating units of the data, and storing the units of the data into one or more physical blocks.
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
Memory controller, bridge device and method for transferring command and data between memory controllers
A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller includes a second transmission interface. The first transmission interface and the second transmission interface are flash memory interfaces. In a program mode, the first transmission interface receives a first command from the second transmission interface and obtains first transfer data from a bus in response to the first command. A value of the first command is optionally set to a first value or a second value. The first value indicates a memory command transfer operation in a first direction and the second value indicates a memory data transfer operation in the first direction. The first transmission interface processes the first transfer data according to the value of the first command to obtain a memory command or written data.