Patent classifications
G06F3/0653
TEMPERATURE READINGS FOR MEMORY DEVICES TO REDUCE TEMPERATURE COMPENSATION ERRORS
A system includes a memory array, a thermometer, and control logic, operatively coupled with the memory array and the thermometer, to perform operations including causing the thermometer to obtain a first temperature result, monitoring a time since obtaining the first temperature result, determining whether the time satisfies a threshold time condition, in response to determining that the time satisfies the threshold time condition, causing the thermometer to obtain a second temperature result from an automatic temperature reading, determining a difference between the second temperature result and a previously stored temperature result, and filtering the second temperature result based on the difference to obtain a new stored temperature result.
BALANCING POWER, ENDURANCE AND LATENCY IN A FERROELECTRIC MEMORY
Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).
DATA STORAGE WITH MULTI-LEVEL READ DESTRUCTIVE MEMORY
A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.
ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES
A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.
Dynamic Selective Filtering of Persistent Tracing
An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to receive, by a trace filter system, a trace chunk from a trace buffer associated with a processor core in a processing device, where the trace buffer is comprised of a plurality of trace chunks, to filter, by the trace filter system, the trace chunk, and to store the filtered trace chunk in the trace buffer.
Memory system for handling program error and method thereof
A scheme for handling program errors is provided for a memory system which includes a memory device and a controller including firmware and a memory interface. The firmware issues commands for program operations to the memory interface. After detecting a failed program operation in a particular memory block, the firmware reroutes that program operation to a different location in a different memory block and takes further action to reduce the likelihood of a subsequent error occurring in the same memory block in which the failed program operation occurred.
Distributed storage system for long term data storage
A distributed storage system for the long-term storage of data objects that is implemented utilizing one or more distinct storage sites that may be comprised of system controllers and object storage systems that act in concert to embody a single distributed storage system. A system may include a one or more types and/or instances of object storage systems. A system may include object storage systems that are powered on for a limited time as required to complete queued data operations. A system may further include system controllers associated with logical and/or physical sites that coordinate object, user, device, and system management functionally.
Storage device and method of operating the same
Provided herein may be a storage device configured to check a status of a memory device based on data read without output of a status check command, and determine a subsequent command to be generated. The storage device may include a memory device and a memory controller configured to control the memory device. The memory device may include a read data generator configured to generate new read data including both read data corresponding to a read command received from the memory controller and information indicating a status of the memory device. The memory controller may include: a status information determiner configured to determine the status of the memory device based on the new read data received from the read data generator and generate status information and a command generator configured to generate a command to be output to the memory device based on the status information.
Request throttling in distributed storage systems
The disclosed technology includes an example system that has a request throttling manager that is configured to receive a first file data request, queue the first file data request in a first request queue, and process the first file data request based on the first token bucket. The first token bucket includes a sufficient first quantity of first tokens to process the first file data request. The system further includes a storage manager configured to access one or more storage nodes of a plurality of storage nodes of a distributed storage system in response to the first file data request.
Temporarily limiting access to a storage device
Temporarily limiting access to a storage device, including: determining that a storage device of a plurality of storage devices in a storage system is operating outside of a defined performance range; determining that the storage device operating outside of the defined performance range may be caused by a rehabilitative action performed on the storage device; and modifying a storage operation issuance policy for one or more storage devices of the plurality of storage devices until a determination that the storage device is operating within the defined performance range.