A method includes performing a memory operation to access memory cells of a memory sub-system. The method can further include determining, for the memory operation, a quantity of memory cells available to be accessed during the performance of the memory operation. The method can further include determining that a quantity of memory cells that are accessed during the performance of the memory operation comprises fewer than the quantity of memory cells available to be accessed. The method can further include incrementing a counter in response to the determination that the quantity of memory cells accessed is fewer than the quantity of memory cells available to be accessed.

A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.

Techniques are provided for compacting indirect blocks. For example, an object is represented as a structure comprising data blocks within which data of the object is stored and indirect blocks comprising block numbers of where the data blocks are located in storage. Block numbers within a set of indirect blocks are compacted into a compacted indirect block comprising a base block number, a count of additional block numbers after the base block number in the compacted indirect block, and a pattern of the block numbers in the compacted indirect block. The compacted indirect block is stored into memory for processing access operations to the object.

Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may include a buffer memory for storing tail doorbell information for N submission queues capable of storing a command fetched from the host or head doorbell information for N completion queues capable of storing an execution result of the command fetched from the host.

A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store a head pointer and a tail pointer of one or more first queues; and an entry buffer configured to store a first command from one of the one or more first queues in the entry buffer, wherein the processing circuitry is configured to, determine an order in which the commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in one of one or more second queues.

A data processing method for a network adapter includes the network adapter that obtains a first input/output (I/O) command. The first I/O command instructs to write data stored in a local server to at least one remote server, and the first I/O command includes address information and length information that are of the data and that are stored in the local server. The network adapter splits the data based on the address information and the length information to obtain a plurality of groups of address information and length information. The network adapter obtains, from the local server based on the groups of address information and length information, data corresponding to the groups of address information and length information, and sends the data to the at least one remote server.

A system and method for low-distortion compaction of floating-point numbers comprising a pre-encoder, a data deconstruction engine, a library manager, a codeword storage, and a data reconstruction engine. A pre-encoder may receive a plurality of data sourcepackets with may contain one or more floating-point numbers and the received data sourcepackets are scanned to identify floating-point numbers and the identified floating-point numbers. Identified floating-point numbers may be pre-encoded into binary string representations which are low-distortion embeddings of real numbers into a Hamming space. The binary string representation may be indexed to indicate it represents a floating-point number before being compacted by a data deconstruction engine and library manager. The pre-encoding of floating-point numbers located within a sourcepacket enables the system to maximize the benefit of the compaction capabilities of the data deconstruction engine.

One example method includes optimizing client-side deduplication. When backing up a client, an overwrite ratio is determined based on a size of actual changes made to a volume and a size indicated by changes in a change log. Client-side deduplication is enabled or disabled based on a value of the overwrite ratio.

A processor includes a first processing unit, a second processing unit, a third processing unit, a system control unit, and a storage unit. The first processing unit is configured to obtain data transmitted to the processor and determine whether the data is to be processed by the first processing unit, the second processing unit, or the third processing unit. The second processing unit is configured to execute a neural network algorithm. The third processing unit is configured to perform a feature extraction algorithm on the data. The system control unit is configured to control power supply information of each of the first processing unit, the second processing unit, and the third processing unit. The storage unit is configured to store at least data processing algorithms performed by the first processing unit, the second processing unit, and the third processing unit.