A system and method for managing data in a ring buffer is disclosed. The system includes a legacy ring buffer functioning as an on-chip ring buffer, a supplemental buffer for storing data in the ring buffer, a preload ring buffer that is on-chip and capable of receiving preload data from the supplemental buffer, a write controller that determines where to write data that is write requested by a write client of the ring buffer, and a read controller that controls a return of data to a read client pursuant to a read request to the ring buffer.

A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.

A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.

This information processing system inputs/outputs data normally, even when a serial communication bus is extended by network communication. The information processing system is provided with: a device; a device control unit for controlling the device; a device interface unit which interfaces with the device control unit; an information processing device provided with an application interface unit which interfaces with an application; a channel establishment unit which connects, via a communication unit, the application interface unit and the device interface unit, and establishes a control channel and a data channel between the application and the device; and an error suppression unit which suppresses the occurrence of error in data transfer over the channel established by the channel establishment unit.

This information processing system inputs/outputs data normally, even when a serial communication bus is extended by network communication. The information processing system is provided with: a device; a device control unit for controlling the device; a device interface unit which interfaces with the device control unit; an information processing device provided with an application interface unit which interfaces with an application; a channel establishment unit which connects, via a communication unit, the application interface unit and the device interface unit, and establishes a control channel and a data channel between the application and the device; and an error suppression unit which suppresses the occurrence of error in data transfer over the channel established by the channel establishment unit.

This application discloses a data flow control method and apparatus. The method includes: calculating, by a device when a clock signal arrives, a quantity of transition-minimized differential signaling (TMDS) characters currently stored in a buffer of the device; and outputting, by the device, the TMDS character in the buffer when the quantity of TMDS characters currently stored in the buffer reaches a preset value, or outputting a gap data packet when the quantity of TMDS characters currently stored in the buffer does not reach a preset value, where the preset value is less than or equal to a TMDS character storage capacity of the buffer.

A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.