A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

An electronic device that compresses data and an operating method thereof are provided. The electronic device includes a processor configured to express each of a plurality of data according to a floating-point format that includes a sign field, an exponent identifier field, and a mantissa field, wherein an exponent identifier field included in each of the plurality of data includes a bit value that represents any one of a plurality of exponents.

An electronic device that compresses data and an operating method thereof are provided. The electronic device includes a processor configured to express each of a plurality of data according to a floating-point format that includes a sign field, an exponent identifier field, and a mantissa field, wherein an exponent identifier field included in each of the plurality of data includes a bit value that represents any one of a plurality of exponents.

According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands.

According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands.

An adder and a method for calculating 2.sup.n+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2.sup.n+x for x<0 and 2.sup.n−1≤|x|<2.sup.n+1; a second path configured to calculate 2.sup.n+x for |x|<2.sup.n; a third path configured to calculate 2.sup.n+x for |x|≥2.sup.n; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

An adder and a method for calculating 2.sup.n+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2.sup.n+x for x<0 and 2.sup.n−1≤|x|<2.sup.n+1; a second path configured to calculate 2.sup.n+x for |x|<2.sup.n; a third path configured to calculate 2.sup.n+x for |x|≥2.sup.n; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.

When the conversion arithmetic of the numerical type of floating-point data and integer data is performed by software, the load of the CPU becomes heavy. A semiconductor device includes a memory, a bus coupled to the memory, a bus master coupled to the bus, and a conversion arithmetic circuit coupled to the bus. The conversion arithmetic circuit includes a floating-point data adder-subtracter, an integer data adder-subtracter, and a shift operator. The semiconductor device converts the floating-point data to the integer data or converts the integer data to the floating-point data, without employing a multiplier and a divider of the floating-point data.

When the conversion arithmetic of the numerical type of floating-point data and integer data is performed by software, the load of the CPU becomes heavy. A semiconductor device includes a memory, a bus coupled to the memory, a bus master coupled to the bus, and a conversion arithmetic circuit coupled to the bus. The conversion arithmetic circuit includes a floating-point data adder-subtracter, an integer data adder-subtracter, and a shift operator. The semiconductor device converts the floating-point data to the integer data or converts the integer data to the floating-point data, without employing a multiplier and a divider of the floating-point data.