An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

An information processing device includes a storage unit and a processing circuit. The storage unit is configured to store a first variable and the second variable. The processing circuit is configured to update a first vector having the first variable by weighted addition of the corresponding second variable to the first variable, update a second vector having the second variable by weighting the first variable with a first coefficient that monotonically increases or monotonically decreases depending on the number of updates, adding the weighted first variable to the corresponding second variable, calculating a problem term using a plurality of the first variables, and adding the problem term to the second variable, and repeat updating of the first vector and the second vector, then initialize the second variable of the second vector using a pseudo random number, and then repeat updating of the first vector and the second vector again.

A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of −1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of 1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.