In one aspect, A method for computing neural network computation includes the step of, providing plurality of neurons, coupled with a plurality of inputs, through a plurality of synapses. Each neuron output is given by an equation Σ(X.sub.i*Y.sub.i)+b. X.sub.i*Y.sub.i comprises the ith synapse of the neuron. X.sub.i comprises a set of X.sub.i input vectors. Each X.sub.i input vector is translated into an equivalent electrical signal for an ith corresponding synapse of the plurality of neurons, Y.sub.i comprises a set of Yi weight vectors, wherein each Y.sub.i weight vector comprises a parameter for the ith corresponding synapse of the plurality of neurons. Each synapse is a sub-system and the sub-system comprises a negative vector neural circuit, a positive vector neural circuit, and a set of four non-volatile memory weight cells for computation. The method includes the step of identifying the input vector x as a positive input vector or a negative input vector.

An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained based on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.

The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits also depends upon the value of the first sample.

Systems, apparatuses, and methods related to acceleration circuitry are described. The acceleration circuitry may be deployed in a memory device and can include a memory resource and/or logic circuitry. The acceleration circuitry can perform operations on data to convert the data between one or more numeric formats, such as floating-point and/or universal number (e.g., posit) formats. The acceleration circuitry can perform arithmetic and/or logical operations on the data after the data has been converted to a particular format. For instance, the memory resource can receive data comprising a bit string having a first format that provides a first level of precision. The logic circuitry can receive the data from the memory resource and convert the bit string to a second format that provides a second level of precision that is different from the first level of precision.

The invention relates to the representation of digital signals. In order to improve the perception by a user of the quality of a digital signal, a first sample of first digital signal is approximated to a second sample of a second digital signal having a second number of significant bits lower than the first number of significant bits of the first sample. The second number of significant bits is also lower than a number of significant bits allowing the second digital signal, or a signal derived therefrom to match an expected bit depth of a processing unit said second digital signal, or a signal derived therefrom is to be sent to.

The invention relates to improved convolutions of digital signals. When a first digital signal is convoluted with a second digital signal to obtain an output digital signal, to be converted afterwards using a limited number of bits. In order to prevent a loss of information, and therefore a degradation of the output digital signal upon the future conversion, at least one of the first and the second digital signal is formed of suitable values that store the information from the first digital signal within the most significant bits of the output digital signal.

The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.

An approach is provided for embedding information into probe data. The approach involves retrieving a probe data set comprising a plurality of probe data points collected from a probe device. The approach also involves determining the information to embed, wherein the information is a bit string of a specified length. The approach further involves iteratively selecting at least one bit of the bit string to embed into at least one probe data point of the plurality of probe data points to generate an embedded probe data set until at least a predetermined portion of the bit string is embedded. The approach further involves providing the embedded probe data set as an output

An information processing device, includes a memory; and a processor coupled to the memory and configured to: calculate a quantization error when a variable to be used in a neural network is quantized, generate a threshold value based on reference information related to a first recognition rate obtained by past learning of the neural network and a second recognition rate that is obtained by calculation of the neural network, determine a variable of data type to be quantized among variables to be used for calculation of the neural network based on the calculated quantization error and the generated threshold value, and execute the calculation of the neural network by using the variable of data type.

An operation processing apparatus includes a memory and a processor coupled to the memory. The processor executes an operation according to an operation instruction, acquires statistical information for a distribution of bits in fixed point data after an execution of an operation for the fixed point data according to an acquisition instruction, and outputs the statistical information to a register designated by the acquisition instruction.