An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

An energy-efficient multiplication circuit uses analog multipliers and adders to reduce the distance that data has to move and the number of times that the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula generate a matrix multiplication result in form of a current that is then digitized for further processing.

A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

An integrated circuit includes a first logic gate configured to receive a first input signal and a second input signal, and generate a first control signal based on a first bit of first input signal and a first bit of the second input signal obtained in a current cycle. The integrated circuit includes a first backup storage component configured to store a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle. The integrated circuit includes a plurality of first macros each configured to selectively compute, based on the first control signal, a first multiply-accumulate (MAC) value for the first bit of the first input signal and the first bit of the second input signal.

An integrated circuit includes a first logic gate configured to receive a first input signal and a second input signal, and generate a first control signal based on a first bit of first input signal and a first bit of the second input signal obtained in a current cycle. The integrated circuit includes a first backup storage component configured to store a second bit of the first input signal and a second bit of the second input signal obtained in a previous cycle. The integrated circuit includes a plurality of first macros each configured to selectively compute, based on the first control signal, a first multiply-accumulate (MAC) value for the first bit of the first input signal and the first bit of the second input signal.

An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.