A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.

In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.

Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

Example compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store look-up-table (LUT) entries for use in a multiply and accumulate (MAC) operation.

It is desired to provide a technique capable of reducing the time and the power consumption required for computation. Provided is an information processing apparatus including a storage control unit that writes data read from a read target area of an external memory having multiple dimensions to a storage area having the multiple dimensions and a processing unit that executes processing based on the data of the storage area, in which the storage control unit moves the read target area in a first dimension direction in the external memory and performs first overwrite of a back end area of the storage area in a direction corresponding to the first dimension direction with data of a front end area of the read target area after movement in the first dimension direction.

It is desired to provide a technique capable of reducing the time and the power consumption required for computation. Provided is an information processing apparatus including a storage control unit that writes data read from a read target area of an external memory having multiple dimensions to a storage area having the multiple dimensions and a processing unit that executes processing based on the data of the storage area, in which the storage control unit moves the read target area in a first dimension direction in the external memory and performs first overwrite of a back end area of the storage area in a direction corresponding to the first dimension direction with data of a front end area of the read target area after movement in the first dimension direction.

The present disclosure concerns a method of executing a SoftMax function, the method comprising: (i) pre-storing in memory M fraction components (fc.sub.j) in binary form, derived from the expression 2.sup.(j/M), said fc.sub.j forming a lookup table (T) of size M; (ii) calculating, for each z.sub.i, an element y.sub.i of a number of the form 2.sup.y.sup.i; (iii) separating y.sub.i into an integral part (int.sub.i) and a fractional part (fract.sub.i); (iv) determining a lookup index (ind.sub.i) that corresponds to fract.sub.i scaled by the size M; (v) retrieving a fraction component fc.sub.i from T with ind.sub.i; (vi) generating, in a result register, a binary number representative of the exponential value of said z.sub.i, by combining said fc.sub.i retrieved from T and said int.sub.i; (v) adding the K result registers corresponding to z.sub.i into a sum register R7; and (vi) determining the K probability values p.sub.i from the K result registers and the sum register.