Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.

Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.