A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

A method of performing distributed matrix computation using task entanglement-based coding as a method of processing a huge amount of matrix computation in a distributed manner in a distributed computing environment is provided. A main server encodes information to be transmitted to a plurality of edge devices for distributed matrix computation on the basis of task entanglement-based coding employing a Chebyshev polynomial, thereby reducing the amount of information to be transmitted. Also, when the number of computation results received from the edge devices becomes a recovery threshold, the main server immediately performs decoding to derive a matrix computation result.

A method of performing distributed matrix computation using task entanglement-based coding as a method of processing a huge amount of matrix computation in a distributed manner in a distributed computing environment is provided. A main server encodes information to be transmitted to a plurality of edge devices for distributed matrix computation on the basis of task entanglement-based coding employing a Chebyshev polynomial, thereby reducing the amount of information to be transmitted. Also, when the number of computation results received from the edge devices becomes a recovery threshold, the main server immediately performs decoding to derive a matrix computation result.

A neural network device may generate an input feature list based on an input feature map, where the input feature list includes an input feature index and an input feature value, generating an output feature index based on the input feature index corresponding to an input feature included in the input feature list and a weight index corresponding to a weight included in a weight list, and generating an output feature value corresponding to the output feature index based on the input feature value corresponding to the input feature and a weight value corresponding to the weight.

A neural network device may generate an input feature list based on an input feature map, where the input feature list includes an input feature index and an input feature value, generating an output feature index based on the input feature index corresponding to an input feature included in the input feature list and a weight index corresponding to a weight included in a weight list, and generating an output feature value corresponding to the output feature index based on the input feature value corresponding to the input feature and a weight value corresponding to the weight.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

Division is realized with a small number of processing stages. A secure computation apparatus (1) obtains a secret value representing a result of divided N by D using a secret value [N] of a real number N and a secret value [D] of a natural number D. An initialization unit (12) sets a secret value [P.sub.L1] of a partial remainder P.sub.L1 to 0. A parallel comparison unit (13) computes secret values [E.sub.1], . . . , [E.sub.R−1] of comparison results E.sub.1, . . . , E.sub.R−1 of comparing a secret value [n] of a partial divisor n=P.sub.j+1R+N.sub.j with [D]×g for each integer g not less than 1 and less than R in parallel. An update unit (14) computes a secret value [Q.sub.j] of a quotient Q.sub.j and a secret value [P.sub.j] of a partial remainder P.sub.j that satisfy n=DQ.sub.j+P.sub.j using the secret values [E.sub.1], . . . , [E.sub.R−1] of the comparison results E.sub.1, . . . , E.sub.R−1. An iterative control unit (15) executes the parallel comparison unit (13) and the update unit (14) for each integer j from L.sub.1−1 to −L.sub.0.

A method of compressing a set of coefficients for subsequent use in a neural network, the method comprising: applying sparsity to a plurality of groups of the coefficients, each group comprising a predefined plurality of coefficients; and compressing the groups of coefficients according to a compression scheme aligned with the groups of coefficients so as to represent each group of coefficients by an integer number of one or more compressed values.