To carry out evaluation of a road surface property easily and in a short period of time without being costly. Measurement data of a road surface measured for a predetermined road width along a path of a road to be measured is acquired; a unit area having a preset length dimension along the path in the road width is set along the path; a model plane in the unit area is set based on the measurement data at each point in the unit area; point group data is generated from a spaced amount of the model plane and each point in the unit area, visualize and display the spaced amount in the path, and display a result of evaluation obtained through statistical processing with the path shown on a map.

To carry out evaluation of a road surface property easily and in a short period of time without being costly. Measurement data of a road surface measured for a predetermined road width along a path of a road to be measured is acquired; a unit area having a preset length dimension along the path in the road width is set along the path; a model plane in the unit area is set based on the measurement data at each point in the unit area; point group data is generated from a spaced amount of the model plane and each point in the unit area, visualize and display the spaced amount in the path, and display a result of evaluation obtained through statistical processing with the path shown on a map.

A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

Improved computing processor. In an embodiment, one or more roots of a perturbed polynomial equation, comprising a plurality of terms, are computed, assuming a non-zero coefficient for a highest-order one of the plurality of terms. For at least a highest-order term, an error upper bound of an unperturbed coefficient of the term is computed, it is determined whether a perturbed coefficient of the term is less than or equal to the error upper bound, and, when the perturbed coefficient of the term is less than or equal to the error upper bound, one or more roots of the perturbed polynomial equation are computed, assuming a zero coefficient for the term. Each computed root is added to a root set.

Improved computing processor. In an embodiment, one or more roots of a perturbed polynomial equation, comprising a plurality of terms, are computed, assuming a non-zero coefficient for a highest-order one of the plurality of terms. For at least a highest-order term, an error upper bound of an unperturbed coefficient of the term is computed, it is determined whether a perturbed coefficient of the term is less than or equal to the error upper bound, and, when the perturbed coefficient of the term is less than or equal to the error upper bound, one or more roots of the perturbed polynomial equation are computed, assuming a zero coefficient for the term. Each computed root is added to a root set.

A method and a device for finding a square root are provided. The method includes the following steps: storing an unsigned integer into a first register in the form of an N-bit binary code, N being an even number greater than zero; using an operation circuit to determine whether or not the (N−1).sup.th to [N−(2×i)].sup.th bits of the unsigned integer are greater than or equal to the i.sup.th integer square root; if yes, outputting 1 as the value of the [(N/2)−i].sup.th bit of the square root of the unsigned integer and storing the same into a second register; and if not, outputting 0 as the value of the [(N/2)−i].sup.th bit of the square root of the unsigned integer and storing the same into the second register, i being an integer ranging from 1 to (N/2).

A method and a device for finding a square root are provided. The method includes the following steps: storing an unsigned integer into a first register in the form of an N-bit binary code, N being an even number greater than zero; using an operation circuit to determine whether or not the (N−1).sup.th to [N−(2×i)].sup.th bits of the unsigned integer are greater than or equal to the i.sup.th integer square root; if yes, outputting 1 as the value of the [(N/2)−i].sup.th bit of the square root of the unsigned integer and storing the same into a second register; and if not, outputting 0 as the value of the [(N/2)−i].sup.th bit of the square root of the unsigned integer and storing the same into the second register, i being an integer ranging from 1 to (N/2).

Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2.sup.(second input*log.sup.2.sup.(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

A calculation processor for determining a digital output value (OUT) from a digital input value (IN) based on an exponent value a, the processor comprising a first calculation block (CB1), a second calculation block (CB2) and a final calculation block (CBF). The first calculation block (CB1) initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value. The final calculation block is configured to set the output value to the intermediate value.

A calculation processor for determining a digital output value (OUT) from a digital input value (IN) based on an exponent value a, the processor comprising a first calculation block (CB1), a second calculation block (CB2) and a final calculation block (CBF). The first calculation block (CB1) initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value. The final calculation block is configured to set the output value to the intermediate value.