G06F7/556

METHOD FOR GENERATING RANDOM SEQUENCE USING EXPONENTIAL FUNCTION AS RANDOM NUMBER SOURCE
20210382695 · 2021-12-09 · ·

A method for generating a random sequence using an exponential function as a random number source, including: providing an exponential function a.sup.b, wherein, the base a is an integer, and the exponent b is an integer; expanding a value of the exponential function into a first preliminary sequence in decimal; and using the first preliminary sequence as a random number source to generate a random sequence.

Circuitry for Floating-point Power Function

Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2.sup.(second input*log.sup.2.sup.(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

CALCULATION PROCESSOR AND CALCULATION METHOD
20210373853 · 2021-12-02 ·

A calculation processor for determining a digital output value (OUT) from a digital input value (IN) based on an exponent value a, the processor comprising a first calculation block (CB1), a second calculation block (CB2) and a final calculation block (CBF). The first calculation block (CB1) initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value. The final calculation block is configured to set the output value to the intermediate value.

WAVEFORM CONTROLLER TO OPERATE MACHINE
20210373508 · 2021-12-02 ·

A machine control system includes circuitry configured to acquire a second waveform that is generated by exponentiating a first waveform by a real number, and to operate a machine based on the second waveform. The first waveform represents a command of an operation of the machine. The real number has a value other than 0 and 1.

WAVEFORM CONTROLLER TO OPERATE MACHINE
20210373508 · 2021-12-02 ·

A machine control system includes circuitry configured to acquire a second waveform that is generated by exponentiating a first waveform by a real number, and to operate a machine based on the second waveform. The first waveform represents a command of an operation of the machine. The real number has a value other than 0 and 1.

Circuitry for floating-point power function

Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2.sup.(second input*log.sup.2.sup.(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

PROCEDURE TO SPEED-UP VARIATIONAL QUANTUM EIGENSOLVER CALCULATIONS IN QUANTUM COMPUTERS
20220179921 · 2022-06-09 ·

Techniques of facilitating improved computational efficiency in Variational Quantum Eigensolver calculations by quantum computing devices. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise: a distribution component; and a feedback component. The distribution component can set a Pauli-dependent sample budget for a Pauli term of an operator to unevenly distribute a total sample budget for evaluating an expected value of the operator among a plurality of Pauli terms composing the operator. The plurality of Pauli terms can comprise the Pauli term. The feedback component can evaluate compatibility between a prescreening variance for the Pauli term and a production variance of the Pauli term generated using the Pauli-dependent sample budget.

Arithmetic operation circuit

An artificial intelligence system includes a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function. The arithmetic operation circuit includes a first circuit configured to perform an exponent arithmetic operation using a Napier's constant e as a base and output a first calculation result when an exponent in the exponent arithmetic operation is a negative number, wherein an absolute value of the exponent is used in the exponent arithmetic operation, and a second circuit configured to subtract the first calculation result obtained by the first circuit from 1 and output the subtracted value.

Arithmetic operation circuit

An artificial intelligence system includes a neural network layer including an arithmetic operation circuit that performs an arithmetic operation of a sigmoid function. The arithmetic operation circuit includes a first circuit configured to perform an exponent arithmetic operation using a Napier's constant e as a base and output a first calculation result when an exponent in the exponent arithmetic operation is a negative number, wherein an absolute value of the exponent is used in the exponent arithmetic operation, and a second circuit configured to subtract the first calculation result obtained by the first circuit from 1 and output the subtracted value.

LOGARITHM CALCULATION METHOD AND LOGARITHM CALCULATION CIRCUIT
20210365239 · 2021-11-25 ·

The present invention provides a logarithm calculation method, wherein the logarithm calculation method includes the steps of: (a) selecting a first parameter, a second parameter, a third parameter and a fourth parameter corresponding to an i-th iteration operation; (b) determining whether an input value is greater than the third parameter or smaller than the fourth parameter (c) if the input value is greater than the third parameter, updating the input value by multiplying the first parameter, and updating an output value by subtracting a logarithmic value of the first parameter; if the input value is less than the fourth parameter, updating the input value by multiplying the second parameter, and updating the output value by subtracting a logarithmic value of the second parameter (d) adding one to ‘i’ and return to step (a); (e) when ‘i’ is equal to a predetermined value, outputting the current output value.