A host delegates Just-In-Time (JIT) bytecode compilation to a serverless Web Assembly (WASM) runtime. The WASM runtime receives the bytecode, together with any additional arguments (e.g.: offsets of dependent functions, vtable metadata, virtual machine state). The host may include a parser to provide the additional arguments. In response to receiving the bytecode and arguments, the WASM runtime triggers a thread and loads appropriate WASM modules to compile the bytecode. The resulting assembly instructions are sent back to the host for execution in connection with the (frequently requested) method. Only the bytecode of frequently-accessed methods (as determined at the host) may be delegated for compilation. Delegation of bytecodes for compilation according to embodiments, may conserve a significant percentage of CPU cycles at the host, which can then be used for executing code instead. Based upon analysis of historical compilation activities, particular embodiments may pro-actively implement speculative loading of additional WASM modules.

A system and method for the storage within one or more virtual execution context registers private code representative of processes or other information requiring an enhanced degree of security. The storage of the private code can be performed as a function of the type of code or in response to one or more markers embedded within the code. The time-variant nature of the virtual execution context registers affords a high degree of inherent security for the private code data stored within.

The present disclosure relates to a system and a method of optimizing scalar register allocation by a processor. The method comprises receiving an intermediate code and information about one or more available physical registers in a memory of the processor, as input. The method further comprises allocating one or more virtual registers based on the received information, wherein each virtual register is having size of each available physical register. The method also comprises mapping one or more groups of 8-bit location of the one or more virtual registers to one or more register classes. The method further comprises identifying a plurality of scalar variables from the input intermediate code, and dynamically assigning the one or more available physical registers to the identified scalar variables using the one or more register classes.

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

A system and method for register coalescing is described. The system comprises a CORF, a coalescing-aware register file design for GPUs that simultaneously reduces the leakage and dynamic access power, while improving the overall performance of the GPU. CORF achieves these properties by enabling the reads to multiple operands that are packed together to be coalesced, reducing the number of reads to the RF, and improving dynamic energy and performance. CORF combines compiler-assisted register allocation with a reorganized register file (CORF++) in order to maximize operand coalescing opportunities.

An information processing apparatus according to an embodiment includes: a creation processing unit which creates information indicating a message structure based on which a length of a memory area to be secured in a stack area of a virtual address space assigned for a serialization process is determined during compilation; a serialization processing unit which performs a serialization process to serialize data from a device and write the serialized data into a data storage device using the information created by the creation processing unit; and a deserialization processing unit which reads the serialized data written into the data storage device and deserializes the read data using the information created by the creation processing unit.

An electronic device and a control method thereof are disclosed. The electronic device includes: a memory storing input data, and a processor including a first register file and a second register file storing index data corresponding to kernel data, wherein the processor is configured to: based on a first command being input, obtain offset information of valid data included in a part of the index data stored in the first register file, based on the number of pieces of the offset information being greater than or equal to a predetermined number, store data packed with the offset information in a unit of the predetermined number in the second register file, and obtain output data by performing an operation regarding the input data based on the packed data.

A compiler is disclosed. The compiler is configured to generate executable code based on source code, where the source code includes a plurality of variables. The compiler includes an executable code generator configured to allocate a register to each of the source code variables, where the executable code generator is configured to select one of a group of register types to be allocated for each variable, and where the allocated register of each variable corresponds with the determined register type determined therefor.

Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Systems and methods are described for extending a live range for a virtual scalar register during compiling of a program, comprising: receiving an intermediate representation (IR) of a source code configured for implementing single-instruction-multiple-thread (SIMT) execution, the IR representing the source code as control flow graph including a plurality of basic blocks (BB); and when a virtual scalar register defined in a first BB of the IR is last used in a second BB of the IR that is a divergent BB, modifying the IR to extend the live range of the virtual scalar register.