Patent classifications
G06F8/457
Handling Interrupts from a Virtual Function in a System with a Reconfigurable Processor
A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.
Configurable Access to a Reconfigurable Processor by a Virtual Function
A data processing system is presented that includes a communication link, a runtime processor coupled to the communication link, and one or more reconfigurable processors. A reconfigurable processor of the one or more reconfigurable processors is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the arrays of CGR units through the communication link from a physical function driver and from a virtual function driver.
Augmented circuit breaker policy
Disclosed herein are system, method, and device embodiments for enriching the capabilities of an API management product by deploying an augmented circuit breaker policy at an API gateway to automate regression analysis. Based on the augmented circuit breaker policy, the API gateway may perform curative remedies when a triggering condition occurs, e.g. rolling back the software release or alerting administrators. In one use case, the augmented circuit break policy may mitigate the damage of a faulty software release by programmatically directing all requests received at the API gateway to a stable version of the API. The benefits may be extended by using machine learning to train normality models on the typical behavior of a particular API. A user may then configure an augmented circuit breaker policy to perform a programmatic rollback when the API gateway recognizes conditions that diverge from normal behavior.
AUTOMATIC MICROGATEWAY TAXONOMY TAGS
Disclosed herein are system, method, and computer program product embodiments for implementing automatic taxonomy tags in an API microgateway. The API microgateway may receive a plurality of API requests for an API managed by a customer in a period of time and route the plurality of API request to an instance of the API according to a policy of the API. The API microgateway may aggregate metrics information related to the plurality of API requests. The aggregated metrics information may include request features, response features, policy features, and performance features. In response to a cluster of the metrics information corresponding to a tag in a tag prediction system, the aggregated metrics information may be labeled with the tag. The tag and the aggregated metrics information may be added to an access log and sent to the customer.
System and Method for Statistically Distributed Rate Limiting of Application Programming Interface Traffic
Disclosed herein are system, method, and computer program product embodiments for implementing statistical distributed rate limiting in an Application Programming Interfaces (API) Gateway cluster. An API Gateway cluster may comprise a plurality of gateway nodes and manage API traffic to ensure proper function and protect the health of an API. Each gateway node may use a distributed rate limiting algorithm based on the physics formulas for average velocity, average acceleration and distance based on time determine the total number of API requests accepted by all the nodes in the cluster. Implementation of statistical distributed rate limiting allows for accurate estimations of the total requests accepted by cluster without requiring each node to share its status with the other nodes in the cluster upon receiving each API request. This approach allows for minimum computational overhead while prioritizing the health of the API.
GATEWAY CONFIGURATION LANGUAGE FOR USE IN API ENVIRONMENTS
Disclosed herein are system, method, and computer program product embodiments for providing a universal coding language and construct for an application programming language (API) environment. In the environment, a standard language with a predefined and universal format is used for each of the different internal code modules. A translator is then provided in order to translate the standard language to the proprietary language of specific gateways or other vendor products. In some embodiments, a parser is used to in order to convert the code modules to an internal model. The internal model allows a user to visualize or otherwise understand the configuration that has been coded, and to make any necessary modifications.
AUGMENTED CIRCUIT BREAKER POLICY
Disclosed herein are system, method, and device embodiments for enriching the capabilities of an API management product by deploying an augmented circuit breaker policy at an API gateway to automate regression analysis. Based on the augmented circuit breaker policy, the API gateway may perform curative remedies when a triggering condition occurs, e.g. rolling back the software release or alerting administrators. In one use case, the augmented circuit break policy may mitigate the damage of a faulty software release by programmatically directing all requests received at the API gateway to a stable version of the API. The benefits may be extended by using machine learning to train normality models on the typical behavior of a particular API. A user may then configure an augmented circuit breaker policy to perform a programmatic rollback when the API gateway recognizes conditions that diverge from normal behavior.
SYSTEM AND METHOD FOR DEVELOPMENT OF GATEWAY POLICIES IN AN APPLICATION PROGRAMMING INTERFACE ENVIRONMENT
Disclosed herein are system, method, and computer program product embodiments for providing a streamlines API development environment. In the environment, pre-coded code modules corresponding to common policy functions are stored in memory and can be used, copied, and/or incorporated into developer custom policies. Function calls and/or references to specific code modules can be incorporated into developer custom policies, which will invoke one of the stored code modules. Additionally, one or more compilers are provided to compile code from a development language to a predetermined production language. Although the development language is preset by the development environment, other languages can be supported by downloading compilers for preferred development languages.
Prometheus: processing-in-memory heterogenous architecture design from a multi-layer network theoretic strategy
With increasing demand for distributed intelligent physical systems performing big data analytics on the field and in real-time, processing-in-memory (PIM) architectures integrating 3D-stacked memory and logic layers could provide higher performance and energy efficiency. Towards this end, the PIM design requires principled and rigorous optimization strategies to identify interactions and manage data movement across different vaults.
MAPPING METHOD AND MAPPING DEVICE FOR RECONFIGURABLE ARRAY
A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.