A dataflow graph for an application has operation units that are configured to be producers and consumers of tensors. A write access pattern of a particular producer specifies an order in which the particular producer generates elements of a tensor, and a read access pattern of a corresponding consumer specifies an order in which the corresponding consumer processes the elements of the tensor. The technology disclosed detects conflicts between the producers and the corresponding consumers that have mismatches between the write access patterns and the read access patterns. A conflict occurs when the order in which the particular producer generates the elements of the tensor is different from the order in which the corresponding consumer processes the elements of the tensor. The technology disclosed resolves the conflicts by inserting buffers between the producers and the corresponding consumers.

In a data parsing method, a data adapter receives a piece of reference data, wherein the reference data has a data structure, the data structure includes at least one tag and a value corresponding to each of the at least one tag, and the reference data corresponds to a topic. The data adapter establishes a schema for the topic according to at least one path related to at least a portion of the at least one tag and the at least one value of the data structure. Referring to the schema, the data adapter uses a parser to parse a piece of objective data into a piece of parsed data, wherein the objective data has the data structure and corresponds to the topic.

A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.

A design assistance device assists design of a processing device to execute processing and includes an acquirer, divider, communication code generator, and outputter. The acquirer acquires processing code describing content of the processing. The divider divides the processing code into modules and determines, for each of the modules, an execution environment in which the module is to be executed, from among a plurality of execution environments provided on the processing device. The communication code generator generates, when a module of the plurality of modules includes partial processing prioritized for execution in a second execution environment other than a first execution environment determined for execution of the module, a communication code for communication between the first execution environment and the second execution environment to execute the partial processing in the second execution environment. The outputter outputs the plurality of modules and the communication code to the processing device.

Apparatuses, systems, and techniques to detect a manner in which to optimize execution of a matrix operations. In at least one embodiment, a computer system detects a matrix operation and fetches data for the matrix operation before the matrix operation is fetched.

A processor-implemented method for transforming co-routines to equivalent sub-routines is provided. An input is received at a first user device from a user for a first language and a first operating environment. The first language includes the co-routines and is supported in a first hardware environment. The first language is analyzed to transform the co-routines of the first language into the sub-routines of a second language for implementing the co-routines of the first language in a second hardware environment. The second hardware environment supports the sub-routines of the second language in a second operating environment by determining automatic variables for persistent variables and non-persistent variables, transforming the persistent variables and the non-persistent variables into the sub-routines of the second language, determining return statements and yield statements in the co-routines, and translating the co-routines of the first language into the sub-routines of the second language and the second operating environment.

An example embodiment may involve obtaining one or more blueprint files. The blueprint files may collectively define a system of processing nodes, a call flow involving a sequence of messages exchanged by the processing nodes, and message formats of the messages exchanged by the processing nodes. The example embodiment may also involve compiling the blueprint files into machine executable code. The machine executable code may be capable of: representing the processing nodes as decomposed, dynamically invoked units of logic, and transmitting the sequence of messages between the units of logic in accordance with the message formats. The units of logic may include a respective controller and one or more respective workers for each type of processing node.

A design assistance device assists design of a processing device to execute processing and includes an acquirer, divider, communication code generator, and outputter. The acquirer acquires processing code describing content of the processing. The divider divides the processing code into modules and determines, for each of the modules, an execution environment in which the module is to be executed, from among a plurality of execution environments provided on the processing device. The communication code generator generates, when a module of the plurality of modules includes partial processing prioritized for execution in a second execution environment other than a first execution environment determined for execution of the module, a communication code for communication between the first execution environment and the second execution environment to execute the partial processing in the second execution environment. The outputter outputs the plurality of modules and the communication code to the processing device.

A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.

An example embodiment may involve obtaining one or more blueprint files. The blueprint files may collectively define a system of processing nodes, a call flow involving a sequence of messages exchanged by the processing nodes, and message formats of the messages exchanged by the processing nodes. The example embodiment may also involve compiling the blueprint files into machine executable code. The machine executable code may be capable of: representing the processing nodes as decomposed, dynamically invoked units of logic, and transmitting the sequence of messages between the units of logic in accordance with the message formats. The units of logic may include a respective controller and one or more respective workers for each type of processing node.