Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

According to an embodiment, a system can comprise a processor and a memory that can store executable instructions that, when executed by the processor of a first device, can facilitate performance of operations. The operations can comprise receiving, from a second device, a first indication of an operation that was performed on a file stored on the second storage device, and storing an indication of the operation in a data structure, resulting in the data structure storing the first indication and other indications of operations performed on the file. Further, the operations can comprise analyzing indications of operations, comprising the first indication and the second indications, performed on the file stored in the data structure. The operations can further comprise communicating, to the second device, a command to move the file to a third device.

Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

A Vector Element Rotate and Insert Under Mask instruction. Each element of a second operand of the instruction is rotated in a specified direction by a specified number of bits. For each bit in a third operand of the instruction that is set to one, the corresponding bit of the rotated elements in the second operand replaces the corresponding bit in a first operand of the instruction.

Systems, tools, and methods are disclosed that utilize at least one integrated computational element to measure a property of a substance in close proximity to the substance's source. More specifically, systems, tools, and methods are presented that allow the interaction of electromagnetic radiation and the optically-processing of interacted electromagnetic radiation in proximity to an emergence of a fluid from the fluid's source. The integrated computational elements optically-process the interacted electromagnetic radiation into a weighted optical spectrum. The weighted optical spectrum enables the determination of various chemical or physical characteristics of the fluid.

A convolutional neural network hardware acceleration device, a convolutional calculation method, and a storage medium are provided. The device includes an instruction processing element (1), a hardware acceleration component (2), and an external data memory element (3). The instruction processing element (1) decodes instructions, and controls the hardware acceleration component (2) to perform operations corresponding to decoded instructions. The hardware acceleration component (2) includes: an input buffer element (21), a data calculation element (22) and an output buffer element (23). The external data memory element (3) stores the calculation result output by the output buffer element (23) and transmits the data to the input buffer element (21).

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

A system of verifying execution sequence integrity of an execution flow includes a monitoring system in communication with one or more sensors of a system being monitored, where the monitoring system includes one or more electronic devices, and a computer-readable storage medium having one or more programming instructions. When executed, the one or more programming instructions cause at least one of the electronic devices to receive from the sensors, a parameter value for each of one or more parameters that pertain to an operational state of the system, combine the received parameters to generate a combination value, apply a hashing algorithm to the combination value to generate a temporary hash value, search a data store for a result code associated with the temporary hash value, and in response to the result code associated with the temporary hash value indicating that the temporary hash value is incorrect, generate a fault notification.