G06F9/30007

Smart compressor based on adaptive CPU/QAT scheduling method
11431480 · 2022-08-30 · ·

A method, apparatus, and system for assigning the execution of a cryptography and/or compression operation on a data segment to either a central processing unit (CPU) or a hardware cryptography/compression accelerator is disclosed. In particular, a data segment on which a cryptography and/or compression operation is to be executed is received. Status information relating to a CPU and a hardware cryptography/compression accelerator is determined. Whether the operation is to be executed on the CPU or on the hardware accelerator is determined based at least in part on the status information. In response to determining that the operation is to be executed on the CPU, the data segment is forwarded to the CPU for execution of the operation. On the other hand, in response to determining that the operation is to be executed on the hardware accelerator, the data segment is forwarded to the hardware accelerator for execution of the operation.

Instruction and logic to provide vector linear interpolation functionality

Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

Address generation

Various example embodiments for supporting generation of addresses for network entities in communication systems are presented. Various example embodiments for supporting generation of addresses for network entities may be configured to support generation of a new address for a network entity based on an existing address of the network entity. Various example embodiments for supporting generation of addresses for network entities may be configured to support generation of a new address for a network entity based on manipulation of at least a portion of an existing address of the network entity. Various example embodiments for supporting generation of addresses for network entities may be configured to support generation of a transport layer address (e.g., an Internet Protocol (IP) address or the like) for a network entity based on a data link layer address (e.g., a Media Access Control (MAC) address or the like) of the network entity.

HOST OPERATING SYSTEM IDENTIFICATION USING TRANSPORT LAYER PROBE METADATA AND MACHINE LEARNING
20220229669 · 2022-07-21 ·

Techniques, methods and/or apparatuses are disclosed that enable detection of an operating system of a host. Through the disclosed techniques, an operating system detection model, which may be a form of a machine learning model, may be trained to detect operating system. The operating system detection model may be provided to an operating system detector to detect operating system of a host utilizing transport layer probes without the need to have credentialed access to the host.

FPGA chip with distributed multifunctional layer structure

An FPGA chip includes one functional unit, one pre-allocation manager, and wiring segments. The functional unit includes a first module CPE and a second module PLF. The pre-allocation manager may be connected by means of one of the wiring segments. By configuring one pre-allocation manager, data transmission directions of the wiring segments may be changed. The functional unit is connected to one pre-allocation manager by means of a conventional line. The first module CPE and the second module PLF which are adjacent in the same functional unit are connected by means of a cross-connection line. The second functional modules are interconnected by means of a conventional routing system. Different functional blocks can be connected to each other from any position of a circuit.

WORKFLOW RESOURCE MANAGEMENT FOR CLOUD COMPUTING SERVICES
20210373958 · 2021-12-02 ·

A workflow resource manager receives a request to execute a workflow in a cloud computing environment. The workflow resource manager determines that a first set of cloud computing resource requirements associated with the first set of operations for the workflow is satisfied by available cloud computing resources, and responsive to determining that a second set of cloud computing resource requirements associated with a subsequent set of operations for the workflow is not satisfied by the available cloud computing resources, rejects the request to execute the workflow.

ISA ACCESSIBLE PHYSICAL UNCLONABLE FUNCTION

Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.

INSTRUCTION SUPPORT FOR SAVING AND RESTORING KEY INFORMATION
20220207155 · 2022-06-30 ·

Detailed herein is instruction level support to allow untrusted software to save/restore key state from the memory encryption engine to support S3/S4 flows on clients. In a first embodiment, the save/restore is done by the untrusted software and encryption hardware alone. In another embodiment, a security engine (which forms the root of trust on the platform) is involved to protect the keys before handing over to untrusted software. Either embodiment uses the instructions introduced herein which may work differently underneath depending on the implementation option chosen.

ISA ACCESSIBLE PHYSICAL UNCLONABLE FUNCTION
20220209968 · 2022-06-30 ·

Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.

ISA ACCESSIBLE PHYSICAL UNCLONABLE FUNCTION
20220209967 · 2022-06-30 ·

Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.