The disclosure relates to an instruction conversion device, an instruction conversion method, an instruction conversion system, and a processor. The instruction conversion device includes a monitor for determining whether a ready-for-execution instruction is an instruction that belongs to a new instruction set or an extended instruction set, wherein the new instruction set and the extended instruction set have the same type of the instruction set architecture as that of the processor. If the ready-for-execution instruction is determined as an extended instruction, this extended instruction is converted into a converted instruction sequence by means of the conversion system, this converted instruction sequence is then sent to the processor for executions, thereby extending the lifespans of the electronic devices embodied with old-version processors.

Systems, apparatuses and methods may provide for technology that detects one or more local variables in source code, wherein the local variable(s) lack dependencies across iterations of a loop in the source code, automatically generate pipeline execution code for the local variable(s), and incorporate the pipeline execution code into an output of a compiler. In one example, the pipeline execution code includes an initialization of a pool of buffer storage for the local variable(s).

Described embodiments provide systems and methods for augmentation, instrumentation, and other runtime modifications of bytecode-based applications through introduction of static and dynamic hooks. In at least one aspect, described is a system for hooking Java native interface calls from native code to Java code in a Java virtual machine. In at least one aspect, described is a system for static hooking of a Windows Universal application. In at least one aspect, described is a system for dynamically hooking a Windows Universal application.

Methods, apparatus, systems and articles of manufacture are disclosed for intentional programming for heterogeneous systems. An example non-transitory computer readable storage medium includes instructions that, when executed, cause processor circuitry to at least identify a first code block having a first algorithmic purpose based on a second code block having a second algorithmic purpose, the second algorithmic purpose corresponding to the first algorithmic purpose, translate the first code block into executable domain specific language code, and output the executable domain specific language code.

A processing-in-memory (PIM) and a method of outputting an instruction using a PIM. The PIM includes an internal processor, a memory, and a register configured to store instruction meta information. The memory is configured to store a lookup table generated by predicting a future instruction. The external processor is configured to retrieve an instruction corresponding to the instruction meta information from the lookup table in response to a PIM application programming interface (API) call instruction including the instruction meta information. The instruction corresponding to the instruction meta information is output based on a retrieval result.

According to some embodiments, methods and systems may provide integration adapter generation for a cloud computing environment. The system may include a smart adapter user interface component that receives a standard, programming language-agnostic interface specification. The smart adapter user interface component may then graphically interact with a user via a guided navigation, no-code wizard user interface to collect additional information associated with the standard, programming language-agnostic interface specification. A semantic model is then automatically generated by the smart adapter user interface component based on characteristics of the received standard, programming language-agnostic interface specification and the additional information. A smart adapter generator may receive the semantic model along with information about the standard, programming language-agnostic interface specification and automatically generate a Cloud Integration adapter.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process. The process includes storing each of a plurality of generation instructions in a storage area for each of assembly instructions, the generation instructions instructing the generation of instruction sequences of a first instruction set, each instruction sequence of the first instruction set executing a processing equivalent to each assembly instruction of a second instruction set, identifying a first register that is not used by any of the assembly instructions corresponding to the plurality of generation instructions by referring to the storage area, determining a second register of the first instruction set corresponding to the first register as a temporary register in each of the instruction sequences, and generating the instruction sequence that uses the temporary register.

A processor includes an internal memory and processing circuitry. The internal memory is configured to store a definition of a multi-dimensional array stored in an external memory, and indices that specify elements of the multi-dimensional array in terms of multi-dimensional coordinates of the elements within the array. The processing circuitry is configured to execute instructions in accordance with an Instruction Set Architecture (ISA) defined for the processor. At least some of the instructions in the ISA access the multi-dimensional array by operating on the multi-dimensional coordinates specified in the indices.

Methods and systems described herein utilize a jump table in directly-addressable, near code, to facilitate improved execution of frequent calls to executable code from other workloads outside of the near code. By executing a directly-addressable call and jump instruction to access frequently-accessed executable code, indirect call instructions are avoided.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process. The process includes storing each of a plurality of generation instructions in a storage area for each of assembly instructions, the generation instructions instructing the generation of instruction sequences of a first instruction set, each instruction sequence of the first instruction set executing a processing equivalent to each assembly instruction of a second instruction set, identifying a first register that is not used by any of the assembly instructions corresponding to the plurality of generation instructions by referring to the storage area, determining a second register of the first instruction set corresponding to the first register as a temporary register in each of the instruction sequences, and generating the instruction sequence that uses the temporary register.