Non-volatile devices may be configured such that a clear operation on a single bit clears an entire block of bits. The representation of particular data structures may be optimized to reduce the number of clear operations required to store the representation in non-volatile memory. A data schema may indicate that a data structure of an application may be optimized for storage in non-volatile memory. A translation layer may convert an application level representation of a data value associated with the data structure to an optimized storage representation of the data value before storing the optimized storage representation of the data value in non-volatile memory.

Technologies for dynamic statistics management include a computing device with a network interface controller (NIC) and a compute engine having a memory. The NIC is to provision a counter window to a software consumer executing in the computing device. The counter window is used to track a plurality of active counters associated with a network flow. The NIC determines whether one or more flush criteria are triggered. In so determining, the NIC transfers a value for each active counter to the memory, where global counter values are maintained.

A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent. In the execution unit, the memory access instructions are executed according to the send order. This helps avoiding re-execution of a memory access instruction due to an address correlation of the memory access instruction. Consequently, this eliminates the need of adding an idle cycle in an instruction pipeline and the need of refreshing the pipeline to clear a memory access instruction that is incorrectly speculated.

A system and method for processing data using the universal computing element, which is a computing node that could be integrated with any external services of different business domains via an application programming interface (API), is disclosed. Data and processes are bound using universal computing elements and computing modes that use UCE's, and thus provided as finite-state automata with explicit selection of states in real-time operation, thereby facilitating construction of finite-state automata (i.e., processes) to users who are not programmers. Software, computer program, source/object/assembly code, firmware or other reconfigurable logic or signal processing instructions of the present invention include at least one UCE. Advantageously, data processing is organized to reduce impact of inefficient conventional data usage, particularly via data transfer processed innovatively into state format and usage of automata-based programming for data processing.

A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global front end, wherein the instruction sequence includes at least one branch, creating a delayed branch in response to receiving the one branch, and using a front end track table to track both the delayed branch the one branch.

A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.

A microprocessor is shown, in which a branch predictor and an instruction cache are decoupled by a fetch-target queue (FTQ). The FTQ stores at least an instruction address whose branch prediction has been finished by the branch predictor. The instruction addresses queued in the FTQ is to be read out later as an instruction-fetching address for the instruction cache. The instruction address that is input into the branch predictor and used for branch prediction leads the instruction-fetching address.

A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.

Methods and systems for allowing software components that operate at a specific exception level (e.g., EL-3 to EL-1, etc.) to repeatedly or continuously observe or evaluate the integrity of software components operating at a lower exception level (e.g., EL-2 to EL-0) to ensure that the software components have not been corrupted or compromised (e.g., subjected to malware, cyberattacks, etc.) include a computing device that identifies, by a component operating at a higher exception level (“HEL component”), at least one of a current vector base address (VBA), an exception raising instruction (ERI) address, or a control and system register value associated with a component operating at a lower exception level (“LEL component”). The computing device may perform a responsive action in response to determining that the current VBA, the ERT address, or control and system register value do not match the corresponding reference data.