A processor includes: an instruction fetch portion configured to fetch simultaneously a plurality of fixed-length instructions in accordance with a program counter; an instruction predecoder configured to predecode specific fields in a part of the plurality of fixed-length instructions; and a program counter management portion configured to control an increment of the program counter in accordance with a result of the predecoding.

In the field of data reading and writing technologies, a data writing method is associated with a data writing apparatus and an electronic device. The data writing method includes: determining whether a start storage address of a first data block is aligned with a bus bit width of a storage; in response to that the start storage address of the first data block is not aligned with the bus bit width of the storage, determining whether a second data block which is a data block immediately before the first data block is compressed; in response to that the second data block is compressed, executing complete writing on a first beat of the first data block.

An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.

Methods for determining cache activity and for optimizing cache reclamation are performed by systems and devices. A cache entry access is determined at an access time, and a data object of the cache entry for a current time window is identified that includes a time stamp for a previous access and a counter index. A conditional counter operation is then performed on the counter associated with the index to increment the counter when the time stamp is outside the time window or to maintain the counter when the time stamp is within the time window. A counter index that identifies another counter for a previous time window where the other counter value was incremented for the previous cache entry access causes the other counter to be decremented. A cache configuration command to reclaim, or additionally allocate space to, the cache is generated based on the values of the counters.

An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.

A microprocessor with a solution to instruction fetching failure is shown. The branch predictor and the instruction cache are decoupled by a fetch target queue. In response to instruction fetching failure of a target fetching address, the instruction cache regains the target fetching address from the fetch target queue to restart the failed instruction fetching.

Briefly, an encryption/decryption algorithm providing for consistent encryption entropy and encryption/decryption performance that is independent of the type of input data.

Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.

An apparatus and method are provided for managing a capability domain. The apparatus has processing circuitry for executing instructions, the processing circuitry when in a default state being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is also provided to store a program counter capability used by the processing circuitry to determine a program counter value. The program counter capability is arranged to identify a capability state for the processing circuitry. The processing circuitry is then arranged, when the capability state indicates the default state, to operate in the capability domain. However, when the capability state indicates the executive state, the processing circuitry is arranged to operate in a manner less constrained than when in the default state so as to allow modification of the capability domain. This provides a simple and effective mechanism for selectively allowing the apparatus to modify the capability domain.

Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.