Patent classifications
G06F9/3836
System and method for establishing and managing inter-institution transaction system
Disclosed is a method of establishing and managing an inter-institution transaction system. The method comprises creating plurality of threads to constitute parallel fund transfer system, wherein each thread is a replica of single fund transfer system, and wherein plurality of threads are to be operated in parallel; assigning plurality of institutions to plurality of threads, wherein a given institution is assigned as a sending institution and/or a receiving institution of a financial transaction to at least one thread, and a given thread has at least one sending institution-receiving institution pair assigned thereto; assigning financial transactions to plurality of threads based at least on sending institution-receiving institution pairs assigned to plurality of threads; and processing financial transactions at their corresponding threads.
SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.
TECHNIQUES FOR IMPLEMENTING ROLLBACK OF INFRASTRUCTURE CHANGES IN A CLOUD INFRASTRUCTURE ORCHESTRATION SERVICE
Techniques for implementing rollback of infrastructure changes in an infrastructure orchestration service are described. In certain examples, an infrastructure orchestration service is disclosed that manages both provisioning and deploying of infrastructure assets within a cloud environment. The service receives a plan comprising a set of instructions associated with a set of infrastructure assets of an execution target and identifies a first state of the set of infrastructure assets. The service executes the set of instructions in the plan to achieve a second state for the set of infrastructure assets. Based in part on the executing, the service receives a trigger for rolling back the plan to restore the set of infrastructure assets in the plan to the first state and executes a rollback plan for the plan. The service then transmits a result associated with the execution of the rollback plan.
APPARATUS AND METHOD FOR VECTOR PACKED SIGNED/UNSIGNED SHIFT, ROUND, AND SATURATE
Apparatus and method for signed and unsigned shift, round and saturate using different data element values. For example, one embodiment of an apparatus comprises a decoder to decode an instruction having fields for a first packed data source operand to provide a first source data element and a second source data element, a second packed data source operand or immediate to provide a first shift value and a second shift value corresponding to the first source data element and second source data element, respectively, and a packed data destination operand to indicate a first result value and a second result value corresponding to the first source data element and second source data element, and execution circuitry to execute the decoded instruction to: shift the first source data element by an amount based on the first shift value to generate a first shifted data element; shift the second source data element by an amount based on the second shift value to generate a second shifted data element; update a saturation indicator responsive to detecting a saturation condition resulting from the shift of the first and/or second source data elements; round and/or saturate the first and second shifted data elements in accordance with a specified rounding mode and the saturation indicator, respectively, to generate the first and second result data elements; and store the first result value and the second result value in a first data element location and a second data element location in a destination register.
Systems and Methods for Scaling Volumes Using Volumes Having Different Modes of Operation
A method, a computing device, and a non-transitory machine-readable medium for managing modes of operation for volumes in a node. A first portion of a plurality of volumes in a node is selected to operate in an active mode. A second portion of the plurality of volumes in the node is selected to operate in a passive mode. The second portion of the volumes that operates in the passive mode consumes fewer resources than the first portion of the volumes that operates in the active mode. The first portion of the plurality of volumes and the second portion of the plurality of volumes are adjusted over time based on activity of each volume of the plurality of volumes.
Drive control method and apparatus, and display device
Disclosed are a drive control method and apparatus and a display device. The drive control method may be applied to a controller, and include: adding at least one configuration instruction into a target region of one row of data to obtain a target row of data, wherein the configuration instruction is intended for self-configuration of a drive parameter by a first driver chip, and the target region includes at least one of a blank region and a region where display data is located; and sending the target row of data to the first driver chip.
Memory controller and memory system for generating instruction set based on non-interleaving block group information
Embodiments of the present invention include a memory controller including a buffer memory configured to store program data, an instruction set configurator configured to configure an instruction set describing a procedure for programming the program data stored in the buffer memory to target memory blocks, an instruction set performer configured to sequentially perform instructions in the instruction set and generate an interrupt at a time of completion of performance of a last instruction among the instructions, and a central processing unit configured to erase the program data stored in the buffer memory when the interrupt is received from the instruction set performer. The instruction set configurator may configure the instruction set differently according to whether a non-interleaving block group exists among the target memory blocks.
Communicating an event to a remote entity
An example method includes detecting an event in an electronic system. The electronic system includes an electronic component and a switched mode power supply. The electronic component draws an amount of power from the switched mode power supply during operation. In response to detecting the event, the electronic component is operated to cause the electronic component to change the amount of power that the electronic component draws from the switched mode power supply. The change in the amount of power that the electronic component draws causes the switched mode power supply to output a signal that is evidence of the event.
Systems, methods, and apparatuses for tile store
Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.
Optimized branching using safe static keys
Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location. The processing device may determine whether a value of the safe static key is initialized. Responsive to determining that the value of the safe static key is initialized, the processing device may further replace the branching instruction with an unconditional branching instruction specifying the first target location. Responsive to determining that the value of the safe static key is uninitialized, the processing device may replace the branching instruction with a conditional branching instruction specifying the first target location.