A method for starting a system-on-a-chip, SoC, without read only memory, ROM, comprises the steps of receiving, by a processor comprised by the SoC, a reset signal, monitoring, by a monitoring component comprised by the SoC, a connection between the processor and at least a non-volatile memory, both comprised by the SoC, upon occurrence of a first read access of the processor to the non-volatile memory via the connection checking, by the monitoring component, whether a data value returned in response to the first read access via the connection conforms to a pre-set value, and if the returned data value differs from the pre-set value, stopping, by the monitoring component, operation of the processor.

Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

In an embodiment, a system includes a contactless reader and an apparatus. The apparatus includes a contactless transponder including a contactless interface and a transponder wired interface and being configured to communicate with a contactless reader according to a contactless protocol through the contactless interface. The apparatus includes a bus coupled to the transponder wired interface, and at least one module coupled to the bus, the at least one module including a processing circuit, the contactless reader being configured to communicate instructions of a software program executable by the processing circuit to the at least one module through the contactless transponder.

A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores an extreme memory profile (XMP). When the processor performs the BIOS so that the computer device displays a user interface (UI), the BIOS displays an overclocking option corresponding to the XMP in a selection list of the UI. When the BIOS receives a selection request corresponding to the overclocking option of the selection list, the BIOS reads multiple memory setting parameters corresponding to the XMP, and configures the memory module according to the memory setting parameters.

A micro-controller chip is coupled to an external memory and includes a central processing unit (CPU), an address reorder circuit, and an address bus. The CPU is configured to provide a first internal address. The address reorder circuit calculates a unique identifier and a seed code to generate a base parameter and performs a reorder operation for the first internal address according to the base parameter to generate a first encryption address. The address bus is coupled between the address reorder circuit and the external memory to provide the first encryption address to the external memory. The external memory stores specific data according to the first encryption address.

An information processing apparatus includes a storage unit configured to store at least a first boot program and a second boot program corresponding to the first boot program, a controller configured to read and execute a program, detect, in accordance with occurrence of a read error at reading of the first boot program, an address of a storage area storing a program in which the read error has occurred in the first boot program, and specify, from an address of a storage area storing the second boot program, an address corresponding to the detected address. The controller reads and executes the second boot program stored in the specified address.

The present disclosure relates to a method, device and computer program product for executing a job in an application system. Here, the application system comprises a first processing device and a second processing device, and a first response speed of the first processing device being lower than a second response speed of the second processing device. In a method, a job request is received from a user of the application system, the job request specifying that the job is to be executed in the application system; a job type of the job is determined, the job type describing a requirement of the user on a response speed for executing the job; a target processing device is selected from the first processing device and the second processing device in accordance with determining that the job type relates to a high response speed; and the job is assigned to the selected target processing device, so that the job is executed by the target processing device. By means of the above method, a processing device for processing a job is selected based on the type of the job, and further processing devices in the application system may be dispatched more effectively. Furthermore, there is provided a corresponding device and computer program product.

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence. In one embodiment, the peripheral device is a Non-Volatile Memory Express (NVMe)-compliant data storage device.

A pulse counting apparatus operating at a low power and an operation method thereof are provided. The pulse counting apparatus includes a pulse counter configured to count a number of pulses inputted from outside of the pulse counting apparatus and generate an interrupt signal; a timer unit configured to generate a wake-up signal according to a preset time; a real time clock (RTC) configured to serve as a clock of the pulse counter and the timer unit; and a processor configured to switch from a sleep mode to an active mode when the interrupt signal or the wake-up signal is generated.