A method for initializing a bus system for a process plant includes: installing an administrative bus participant and a second bus participant at respective installation sites in the process plant; storing a list of at least two installation sites of bus participants in the administrative bus participant; connecting the administrative bus participant and the second bus participant to each other across a data bus; prompting an identification sensor of the second bus participant with an identification prompt; after detection of the identification prompt by the identification sensor, sending an identification signal identifying the second bus participant to the administrative bus participant; and after receiving the identification signal identifying the second bus participant, matching up the second bus participant with an installation site of the at least two installation sites contained in the stored list.

A method for controlling a technical system, in particular of a motor vehicle.

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

Apparatuses, systems, and techniques to configure processor partitioning for a multi-process service. In at least one embodiment, a multi-process service configures a set of streaming multiprocessors of one or more parallel processing units to perform one or more threads based on one or more user-defined data values accessible to a parallel processing library, such as compute uniform device architecture (CUDA).

Facilitating per-CPU reference counting for multi-core systems with a long-lived reference is provided herein. A system includes a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations include determining a first quantity of releases associated with an object in a data structure of the system and determining a second quantity of acquisitions associated with the object. The first quantity of releases can be distributed among respective first counters of processing elements of a group of processing elements. The second quantity of acquisitions can be distributed among respective second counters of the processing elements of the group of processing elements. Further, the operations can include, based on the second quantity of acquisitions and the first quantity of releases being determined to be a same value, implementing a removal of the object from the data structure.

A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

During operation, an electronic device receives a packet or a frame associated with a second electronic device, where the packet or the frame includes information specifying a factory reset command. For example, the second electronic device may be a dynamic host configuration protocol (DHCP) server or may perform functions of a DHCP server. Moreover, the packet or the frame may include an acknowledgment (ACK) in a discover, offer, request and acknowledgment (DORA) procedure, and the information may be included in an option 43 subfield or an option 52 subfield in the packet or the frame. In response to receiving the factory reset command, the electronic device performs a factory reset. Note that the factory reset may restore firmware in the electronic device to a factory-fresh version and a configuration of the electronic device to a factory-fresh state, may erase memory in the electronic device.

A system and method for facilitating management of edge computing nodes of an edge computing network is disclosed is disclosed. The method includes registering one or more second edge nodes with an edge computing network, reading a MAC address of a network card associated with the one or more second edge nodes, and obtaining installation topic and the MAC address. Also, the method includes publishing a message on the installation topic associated with one or more parameters, performing one or more operations on the set of first edge nodes based on the installation topic, and executing the set of install instructions on the one or more second edge nodes. Further, the method includes publishing a result of the execution of the set of install instructions on the installation topic and the MAC address and updating a state of the edge computing network.

A system booting method for a computer system having a plurality of central processing units and a booting unit is disclosed. The system booting method includes determining, by the booting unit, a booting mode of the computer system; transmitting a booting signal, which is related to the booting mode, to the plurality of CPUs of the computer system; and entering a multi-CPU booting mode or entering an independent booting mode of the plurality CPUs according to the booting signal.

A processor includes at least one socket and at least one memory. Each socket includes a first die and a second die. The first die receives a boot-enable signal and an internal boot-enable signal to execute a boot procedure, and outputs a boot-completion signal after completing the boot procedure. The second die receives the internal boot-enable signal and the boot-completion signal from the first die to execute the boot procedure. The second die is electrically connected to the first die through a communication bus. The memory is electrically connected to the second die. When the first die executes the boot procedure, the first die accesses the memory through the communication bus and the second die.