Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

A system, method and program product that provides a conversational AI platform using a declarative graph model. A system is included having a natural language (NL) interface the receives NL user inputs from a message queue; an intent analyzer that determines an intent of a received NL user input and loads a graph associated with the intent; and a graph traversal manager having traversal logic to first traverse the graph first along a start path from an intent node to a dialog node, then traverse an ask path to a question node to obtain missing entity data, then traverse a contacts path to a service node to execute an external service and return a fulfillment response based on submitted entity data, then traverse a replies with path to a response node to create a formatted fulfillment response that is forwarded to the message queue.

Embodiments of the disclosure are directed to systems and methods to process a declaratively-specified computer application by interpreting a structure and a behavior specification. Application data items are interpreted using a processing concrete model based on the structure specification. Application functionality is provided by processing the application data items in accordance to the behavior specification. The application information may further be used in an embodiment of the disclosure to perform additional processing and provide an added functionality. Various embodiments of the disclosure allow additional functions for declarative application such as performing domain activities, accessing data items, transferring application data, storing data and milestones and rendering data items.

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

A system, method and program product that provides a conversational AI platform using a declarative graph model. A system is included having a natural language (NL) interface the receives NL user inputs from a message queue; an intent analyzer that determines an intent of a received NL user input and loads a graph associated with the intent; and a graph traversal manager having traversal logic to first traverse the graph first along a start path from an intent node to a dialog node, then traverse an ask path to a question node to obtain missing entity data, then traverse a contacts path to a service node to execute an external service and return a fulfillment response based on submitted entity data, then traverse a replies with path to a response node to create a formatted fulfillment response that is forwarded to the message queue.

Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.