A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Techniques are described for copying data only from a subset of memory locations allocated to a set of instructions to free memory locations for higher priority instructions to execute. Data from a dynamic portion of one or more general purpose registers (GPRs) allocated to the set of instructions may be copied and stored to another memory unit while data from a static portion of the one or more GPRs allocated to the set of instructions may not be copied and stored to another memory unit.

In an approach for locating, preserving, and receiving registers, a register located within a central processing unit is modified a preservation bit, wherein the preservation bit designates when the register is to be preserved. The preservation bit of the register is activated. A preservation bit requests a subroutine to access content held on the register. A register is pushed to a memory source. The bitmask is pushed to a memory source, wherein the bitmask contains information regarding the content pushed to the memory source. The bitmask is popped, at the request of the subroutine, to determine that that content is to be popped. The content is popped from the memory source to the register. The content is returned from the subroutine.

A computing device includes a plurality of registers that store therein information that is used by a process to execute processing. When a process which is executed is switched from a first process to a second process and when the second process does not plan to use a second register in the plurality of registers, the computing device saves information stored in a first register that is being used by the first process into the second register. when the second process plans to use the second register, the computing device saves information stored in the first register into a memory.

A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.

Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.

In a microprocessor having an instruction execution unit and first and second sets of process execution resources, context information for a process next-to-be-executed by the instruction execution unit is loaded into a register file, translation lookaside buffer and first-level data cache of the first set of process execution resources during a first interval. During the first interval and concurrently with the loading of context information for the process next-to-be executed, the instruction execution unit executes a current process, including accessing context information for the current process within the register file, translation lookaside buffer and first-level data cache of the second set of process execution resources.