For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

Techniques are disclosed relating to scheduling program tasks in a server computer system. An example server computer system is configured to maintain first and second sets of task queues that have different performance characteristics, and to collect performance metrics relating to processing of program tasks from the first and second sets of task queues. Based on the collected performance metrics, the server computer system is further configured to update a scheduling algorithm for assigning program tasks to queues in the first and second sets of task queues. In response to receiving a particular program task associated with a user transaction, the server computer system is also configured to select the first set of task queues for the particular program task, and to assign the particular program task in a particular task queue in the first set of task queues.

In example implementations, an apparatus is provided. The apparatus includes a context switch block, a processor performance state block, and a task execution block. The context switch block is to perform a context switch. The processor performance state block is to load a processor with a processor performance state stored in a context information associated with a task. The task execution block is to execute the task with the processor operating at the processor performance state loaded from the context information.

Overhead associated with data re-protection during scaling out and/or scaling up of a distributed cloud storage system can be reduced. A coding matrix that is to be utilized for erasure coding in a potential final configuration of the distributed cloud storage can be determined. During initial data protection, a portion of the coding matrix can be utilized to determine coding chunks for protecting data chunks stored within different geographical zones of the distributed cloud storage system. When additional zones are added to the distributed cloud storage system, a larger portion of the coding matrix can be utilized to erasure code the new configuration and accordingly, the existing coding chunks are considered as partially complete. Further, the partially complete coding chunks can be combined with data chunks stored within the newly added zones and coefficients of the larger portion of the coding matrix to generate complete coding chunks.

For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task.

An information processing device connectable to a plurality of storage devices includes a power source circuit configured to supply power from a backup power source to each of the plurality of storage devices in response to a power loss event, and a processor. The processor is configured to transmit, to each of the storage devices, a first instruction to save user data that have been transmitted to the storage device and have not been written in a non-volatile manner, in response to the power loss event, and transmit, to at least one of the storage devices, a second instruction to save updated address translation information that corresponds to the user data and has not been reflected in an address translation table, upon receiving a response indicating completion of saving the user data from each of the storage devices.

An information processing apparatus which is capable of reducing the risk of storage device failure. The information processing apparatus is equipped with a storage device that can be accessed a limited number of times. A control unit performs control to write data into the storage device. The control unit determines whether or not to allow writing into the storage device based on an operating state of the information processing apparatus.

A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.

Computer-implemented methods, systems and infrastructure for depositing at least one instruction onto one or more data blocks of a distributed immutable ledger implemented to have a plurality of data blocks connected by way of logical links in a sequential chain. The at least one instruction may be associated with information deposited onto the one or more data blocks, the deposited information comprising at least one of data or metadata utilizable by a second party, using a computing application, to perform one or more operations according to the at least one instructions as related to a first step in a process being managed by the first party.