A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

Concurrent threads may be synchronized at the level of the memory words they access rather than at the level of the lock that protects the execution of critical sections. Each lock may be associated with an array of flags and each flag may indicate ownership of certain memory words. A pessimistic thread may set flags corresponding to memory words it is accessing in the critical section, while an optimistic thread may read the corresponding flag before any memory access to ensure that the flag is not set and that therefore the associated memory word is not being accessed by the other thread. Thus, optimistic threads that do not have conflicts with the pessimistic thread may not have to wait for the pessimistic thread to release the lock before proceeding.

A method, computer program product, and computer system for receiving an XCopy command is provided. The XCopy command may be in the form of an IO operation. The IO operation may be a subextent block operation. A source range and a destination range of the XCopy command may be determined to be aligned within an alignment boundary. The Xcopy command may be determined to be smaller than a predetermined size. In response to determining the source range and destination range of the XCopy command are aligned within the alignment boundary and the XCopy command is smaller than a predetermined size, the XCopy command may be processed. The receiving of the XCopy command may be recorded in a log.

Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

Methods and apparatus relating to logical resource partitioning via realm isolation are described. In an embodiment, a logic processor, to be assigned to one of a plurality of processor cores of a processor, executes one or more operations for at least one of a plurality of logical realms; The plurality of logical realms include a security monitor realm and the security monitor realm includes security monitor logic to maintain a Realm Identifier (RID) for each of the plurality of logical realms. The security monitor logic controls access to each of the plurality of realms based at least in part on the RID for each of the plurality of logical realms. Other embodiments are also disclosed and claimed.

Technology is disclosed for allocating PCIe bus bandwidth to storage commands in a peer-to-peer environment. A non-volatile storage system has a peer-to-peer connection with a host system and a target device, such as a GPU. A memory controller in the storage system monitors latency of PCIe transactions that are performed over a PCIe bus in order to transfer data for NVMe commands. The PCIe transactions may involve direct memory access (DMA) of memory in the host system or target device. There could be a significant difference in transaction latency depending on what memory is being accessed and/or what communication link is used to access the memory. The memory controller allocates bandwidth on a PCIe bus to the NVMe commands based on the latencies of the PCIe transactions. In an aspect, the memory controller groups the PCIe addresses based on the latencies of the PCIe transactions.

Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another atomic command and indicates the location to the processing core. The processing core writes the opcode and operands into the window and indicates to the translation unit that the atomic command is ready. The translation generates an atomic command and issues the command to the distributed computing network for execution. After execution, the distributed computing network provides a response to the translation unit, which provides that response to the core.

This application provides a data processing method and apparatus. The method includes: receiving, by a master storage node, information that is about a first transaction and that is sent by a read-write node, where the information about the first transaction is used to request to perform a write operation on first data stored on the master storage node; determining, by the master storage node, the first data based on the information about the first transaction, and executing the first transaction; generating, by the master storage node, first transaction status metadata when the first transaction ends, where the first transaction status metadata includes identification information of expired data and identification information of the first transaction; and sending, by the master storage node, the first transaction status metadata to at least one read-only node. According to the data processing method and apparatus, a read delay of a read-only node can be eliminated.

A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.

A system for managing abort events of Hardware Transactional Memory (HTM) transactions to an in-memory database, comprising a processor adapted to control a plurality of abort events of a plurality of database transactions held concurrently to a shared in-memory database and a method for managing abort events comprising analyzing a metadata record associated with each potential abort event, where the metadata record comprises a row ID value and a row version value of a certain one of a plurality of rows of a database that is concurrently accessed by an aborting HTM transaction and another HTM transaction, comparing the row ID value and the row version value to a local ID value and a local version value of the aborting HTM transaction and determining a contention condition between the aborting HTM transaction and the other HTM transaction.