Patent classifications
G06F9/524
OBJECT PROCESSING METHOD AND APPARATUS, COMPUTER DEVICE, AND STORAGE MEDIUM
An object processing method may include: acquiring, based on an object interaction request, a current phase change of a current change operation performed on a target object, the current change operation being divided into a plurality of phase changes according to conflict operation types corresponding to operations; determining, according to a target operation type corresponding to the object interaction request and a current relevant operation type corresponding to the current phase change, a conflict check result corresponding to the object interaction request, the target operation type being a type of a target interaction operation requested by the object interaction request; and executing, based on the conflict check result indicating no conflict, the target interaction operation on the target object according to the object interaction request.
LIVELOCK RECOVERY CIRCUIT FOR DETECTING ILLEGAL REPETITION OF AN INSTRUCTION AND TRANSITIONING TO A KNOWN STATE
Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.
DATABASE LOCKNG MECHANISM
A method for preventing race conditions in a database comprises: setting a first numerical entry and a second numerical entry in a database; receiving a first online transaction; responsive to determining a lock of the database is in progress due to a second received online transaction, suspending the first online transaction; removing the lock after the second received online transaction is completed; responsive to determining that the first entry is greater than zero, decrementing the first entry by an amount indicated in the first online transaction; responsive to determining the second entry is greater than zero, decrementing the second entry; processing the first transaction; and generating an online transaction record for the first transaction and storing the generated record in an online transaction database.
OPENTELEMETRY-BASED CIRCUIT BREAKER AUTOMATION
In one embodiment, a device instruments an application to generate OpenTelemetry trace data during execution of the application. The device identifies, based on where the application was instrumented, a particular method of the application. The device determines that a circuit breaker should be inserted for the particular method of the application. The device inserts a circuit breaker for the particular method.
Fine-grained hardware transactional lock elision
Concurrent threads may be synchronized at the level of the memory words they access rather than at the level of the lock that protects the execution of critical sections. Each lock may be associated with an array of flags and each flag may indicate ownership of certain memory words. A pessimistic thread may set flags corresponding to memory words it is accessing in the critical section, while an optimistic thread may read the corresponding flag before any memory access to ensure that the flag is not set and that therefore the associated memory word is not being accessed by the other thread. Thus, optimistic threads that do not have conflicts with the pessimistic thread may not have to wait for the pessimistic thread to release the lock before proceeding.
INTER-KERNEL DATAFLOW ANALYSIS AND DEADLOCK DETECTION
Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.
Multi-Thread Synchronization Method and Electronic Device
A multi-thread synchronization method includes that a first thread requests to obtain a target lock. Then, the first thread checks the lock thread identifier field. The first thread checks the blocked thread quantity field when checking that the lock thread identifier field is a valid thread and is not the first thread. The first thread performs spin wait when checking that the blocked thread quantity field is less than a first threshold. When a quantity of times for spin wait reaches a second threshold and when it is checked that the lock thread identifier field is the valid thread and is not the first thread, the first thread performs an operation of adding 1 to the blocked thread quantity field, and suspends to enter a blocked state.
System and Method for Efficient Snapshots Barrier Mechanism for System With Presorted Container-Based Log
A method, computer program product, and computer system for permitting, by a computing device, entering of a barrier object of a plurality of barrier objects with a first set of one or more Application Programming Interfaces (APIs) only when the barrier object is not set. The first set of the one or more APIs on the barrier object may wait until the barrier object is reset. A second set of the one or more APIs may set the barrier object. Waiting may occur until there are no longer any flows in the barrier object.
SUPPORTING PROCESSING-IN-MEMORY EXECUTION IN A MULTIPROCESSING ENVIRONMENT
A processor for supporting PIM (Processing-in-Memory) execution in a multiprocessing environment includes logic configured to: receive a request to initiate an offload of a number of PIM instructions to a PIM device. The request is issued by a first thread of a processor. The logic is also configured to reserve, based on information in the request, resources of the PIM device for execution of the plurality of instructions.
COMPUTATION OF WEAKLY CONNECTED COMPONENTS IN A PARALLEL, SCALABLE AND DETERMINISTIC MANNER
Disclosed is a configuration to compute weakly connected components (WCCs) in a parallel, scalable and deterministic manner. The configuration receives an undirected original graph having vertices and edges. An undefined value is assigned to all the vertices of the graph. Thereafter, each vertex is visited and assigned a WCCID (index to identify a WCC). The visitation of vertices may determine whether there are one or more thread collisions. A collision is when two threads attempt to identify the same WCC. From these collisions a new graph may be generated, a collision graph, on which the same algorithm is iterated to compute WCCs of that collision graph. The process is iterated until no further collisions are determined. In a post process, the configuration merges the WCCIDs of the collision graphs to produce the WCCIDs of the original graph.