Systems and methods are described for processing ingested data, detecting anomalies in the ingested data, and providing explanations of a possible cause of the detected anomalies as the data is being ingested. For example, a token or field in the ingested data may have an anomalous value. Tokens or fields from another portion of the ingested data can be extracted and analyzed to determine whether there is any correlation between the values of the extracted tokens or fields and the anomalous token or field having an anomalous value. If a correlation is detected, this information can be surfaced to a user.

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host device without halting the execution of the hardware emulator. The software host device can receive the message indicative of the assertion failure event, and execute, asynchronously relative to the execution of the hardware emulator, at least one fail action instruction associated with the assertion failure event.

Data race detection in multi-threaded programs can be achieved by leveraging per-thread memory protection technology in conjunction with a custom dynamic memory allocator to protect shared memory objects with unique memory protection keys, allowing data races to be turned into inter-thread memory access violations. Threads may acquire or release the keys used for accessing protected memory objects at the entry and exit points of critical sections within the program. An attempt by a thread to access a protected memory object within a critical section without the associated key triggers a protection fault, which may be indicative of a data race.

A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Disclosed are an image processing method and an electronic device, which relate to the field of image processing technologies. An electronic device draws a first layer, renders the first layer, and buffers the rendered first layer in a buffer queue. The electronic device finishes drawing the first layer before a first time, and the electronic device draws a second layer, renders the second layer, and buffers the rendered second layer in the buffer queue before the first time, where the first time is a time of arrival of a first vertical synchronization signal for triggering the electronic device to draw the second layer.

An access control method for a shared memory includes: creating and initializing the shared memory, the shared memory initialized including a plurality of region configuration objects, a plurality of block configuration objects and a plurality of data buffers; determining at least one target block according to a volume of data to be written corresponding to a first process; and writing the data by the first process into a target data buffer corresponding to the at least one target block, storing configuration information of the at least one target block to a region configuration object corresponding to a target region, and storing configuration information of the target data buffer to a block configuration object corresponding to the at least one target block.

A system and method for operating a hybrid virtual machine manager are provided. The system includes a master virtual machine manager and one or more slave virtual machine managers, and the master virtual machine manager and the one or more slave virtual machine managers are different types of virtual machine managers The master virtual machine manager is configured to allocate a first type of hardware resource and a second type of hardware resource to the slave virtual machine manager. The first type of hardware resource is a hardware resource capable of being directly operated by the slave virtual machine manager and is used exclusively by the slave virtual machine manager it is assigned to. The second type of hardware resource is a hardware resource that is managed by the master virtual machine manager.

A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Method and device for executing time critical processing in a non-real-time operating system. The method includes capturing a message by a packet capturing tool; analyzing whether the message is a sample value message associated with the time critical processing, and when the message is a sample value message associated with the time critical processing, writing a data unit included in the sample value message into a first buffer; preprocessing the data unit, the preprocessing includes arranging and combining bytes of the data unit so that the bytes indicate sample value is located at specific position; writing the preprocessed data unit from the first buffer into a second buffer and triggering a real-time dedicated thread at the same time, in response to the preprocessed data unit in the first buffer reaching the predetermined number; and executing the time critical processing by reading the preprocessed data unit from the second buffer.