A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.

Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.

Methods and apparatus relating to techniques for an energy-efficient cryptocurrency (e.g., Bitcoin) mining hardware accelerator with a spatially shared message scheduler are described. In an embodiment, a plurality of mining engines perform one or more operations for a cryptocurrency. A single scheduler processes a first portion of a message for two or more mining engines of the plurality of mining engines and pre-computation logic circuitry processes a second portion of the message for the two or more mining engines. Other embodiments are also disclosed and claimed.

Various implementations are described herein for detecting and modifying security settings on a computing device to run a web application using a web browser. A loader application detects security settings on the computing device, determines if the security settings will allow the web application to run and function correctly on the computing device, and if necessary, modifies the security settings to allow the web application to run and operate successfully. Further, described herein are techniques for facilitating communication between components corresponding to a web application running in a web browser and external resources.

A target application loads target application's user interface (UI) after an initial preoperational task is completed. A task for visualizing a progress status for the target application is delegated to a source application that is used for launching the target application in a new window. The source application creates a shared object and assigns a unique identifier (ID) to the shared object. The unique ID of the shared object is passed to the target application, when the target application is launched from the source application. The shared object is accessed by the target application during the performance of the initial preoperational task. The target application stores progress status of the initial preoperational task in the shared object. The source application monitors the progress status stored in the shared object and presents it continuously on source application's user interface.

A central processing unit (CPU) forming part of a computing device, initiates execution of code associated with each of a plurality of objects used by a worker thread. The CPU has an associated cache that is split into a plurality of slices. It is determined, by a cache slice allocation algorithm for each object, whether any of the slices will be exclusive to or shared by the object. Thereafter, for each object, any slices determined to be exclusive to the object are activated such that the object exclusively uses such slices and any slices determined to be shared by the object are activated such that the object shares or is configured to share such slices.

The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Disclosed are embodiments for providing batch performance using a stream processor. In one embodiment, a system is disclosed comprising a stream processor configured to process events emitted by an event stream and output processed events; a queue configured to receive the processed events from the stream processor; a spooler configured to read the processed events from the queue and write the processed events to a buffer; and an auditor process configured to extract a written event from the buffer and confirm that the written event matches an event present in the event stream.

A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

Techniques for identifying and processing graymail are disclosed. An electronic message store is accessed. A determination is made that a first message included in the electronic message store represents graymail, including by accessing a profile associated with an addressee of the first message. A remedial action is taken in response to determining that the first message represents graymail.