Scaling of an ordered event stream (OES) based on a characteristic of one or more writer groups is disclosed. Scaling a portion of an OES contemporaneous to writing events into that portion can conserve computing resources in contrast to more conventional scaling techniques. Moreover, scaling an OES contemporaneously with writing events thereto can enable improved management of OES scaling for applications that can both read events from an input portion of an OES and, via interim events and interim portions of an OES, write events to an output portion of an OES. An application instance can therefore simultaneously act as both a reader group and writer group and can manage data via interim OESs, such that effects of passing the data through the interim OESs can be cascaded into a scaling of the output portion of an OES based on the writer group characteristic.

A control program includes acquiring predetermined information saved in a storage region by a first program, by a second program that is launched in accordance with a second operation as to a screen displayed by a third program having been accepted, and executing, in a case where the predetermined information has been acquired, processing based on the predetermined information by the second program.

A client device sends a connection request to a virtual system in a Kubernetes cluster. The connection request identifies the client device and the application to which the request pertains. Based on a tenant associated with the client device, the virtual system connects the client device to an instance of the application. The instance of the application has access to data for the tenant but not for other tenants. Another client device of the tenant sends another connection request to the virtual system for a connection to another application. Because the tenant is the same, the instance of the other application may access the same data as the instance of the first application. In this way, applications for a single tenant may share data while maintaining the security of the data from other tenants.

Example techniques related to portable playback device power management. An example implementation involves launching a power coordinator background process, the power coordinator background process having multiple client programs and establishing respective inter-process communication (IPC) mechanisms between the multiple client programs and the power coordinator background process. The implementation further involves receiving, via the established IPC mechanisms from the multiple client programs, messages indicating that the respective client program is ready to suspend, and determining that each client program of the multiple client programs is ready to suspend. The implementation further includes sending instructions to the operating system to kernel suspend. While in kernel suspend, the playback device detects a particular trigger to kernel resume and in response, performs a kernel resume.

Inter-microservice communications are managed through in-memory connection routing. A sending microservice writes a message over a port associated with the connection. The message is routed directly to one or more receiving microservices associated with the connection over their ports associated with the connection. The message may be converted to a different format or multiple different formats through plugins processed when the message is received over the sending microservice's port and before the converting messages are routed over the receiving microservices' ports. The inter-microservice communications are hardware and platform independent or agnostic, such that the microservices associated with the connection can be processed on different hardware and different platforms from one another.

Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The tread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.

Examples provide a method of communication between a client driver and a filesystem server. The client driver executes in a virtual machine (VM) and the filesystem server executes in a hypervisor. The method includes: allocating, by the client driver, shared memory in an address space of the VM for the communication; sending identification information for the shared memory from the client driver to the filesystem server through an inter-process communication channel between the client driver and the filesystem server; identifying, by the filesystem server in cooperation with a kernel of the hypervisor, the shared memory within an address space of the hypervisor, based on the identification information, to create a shared memory channel; sending commands from the client driver to the filesystem server through the shared memory channel; and receiving completion messages for the commands from the filesystem server to the client driver through the shared memory channel.

In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

A method performed by a device (e.g., touch controller) includes deriving a pen position, and transmitting a report indicating the derived pen position to a host computer. The report includes a first area storing position data indicating the derived position and a second area storing non-position data different from the position data. The method includes securing a buffer area for retaining a plurality of the reports in a memory, deriving the pen position at each determined scanning time, and generating a report including the position data indicating the derived position. The method includes storing the report in the buffer area and, in response to obtaining the non-position data, writing the non-position data in the second area of each of one or more of the reports stored in the buffer area. The method includes transmitting the plurality of the reports stored in the buffer area to the host computer.

A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.