An electronic device comprises a first processor and a second processor. An inter-processor communication module is connected to the processors and comprises a high priority mailbox and a low priority mailbox. The first processor sends a high or low priority message to the second processor. The first processor is arranged such that if it has a high priority message to send to the second processor, the first processor places the high priority message in the high priority mailbox and sends an interrupt request to the second processor. However, when the first processor has a low priority message to send to the second processor, the first processor places the high priority message in the low priority mailbox to be checked later without sending an interrupt request to the second processor.

The disclosed system may comprise a mainframe computing resource, a data library, a data processing appliance, and a distributed system. The data library may be securely connected to the mainframe computing resource. The data library may be configured to receive data from the mainframe computing resource via a first interface. The data processing appliance may be configured to read and write data to the data library via a second user interface. The distributed system may be configured to receive data from the data processing appliance. The distributed system may be further configured to process the data based on a workflow from the mainframe computing system.

Methods and apparatus for ultra-secure accelerators. New ISA enqueue (ENQ) instructions with a wrapping key (WK) are provided to facilitate secure access to on-chip and off-chip accelerators in computer platforms and systems. The ISA ENQ with WK instructions include a dest operand having an address of an accelerator portal and a scr operand having the address of a request descriptor in system memory defining a job to be performed by an accelerator and including a wrapped key. Execution of the instruction writes a record including the src and a WK to the portal, and the record is enqueued in an accelerator queue if a slot is available. The accelerator reads the enqueued request descriptor and uses the WK to unwrap the wrapped key, which is then used to decrypt encrypted data read from one or more buffers in memory. The accelerator then performs one or more functions on the decrypted data as defined by the job and writes the output of the processing back to memory with optional encryption.

Described are examples for providing stream augmenting components. A stream augmenting component having an augmentation function indicating a plurality of interfaces to one or more devices and an output stream can be initialized. At least a portion of the plurality of interfaces for the one or more devices can be accessed to at least one of obtain stream output from the one or more devices or control the one or more devices. A plurality of stream outputs from the one or more devices can be virtualized to the output stream at least in part by modifying or correlating data received over the plurality of stream outputs. The stream augmenting component can output the output stream to one or more other stream augmenting components or applications via at least another portion of the one or more interfaces.

Embodiments of the present disclosure provide a data processing method, apparatus, electronic device and computer-readable storage medium. The data processing method includes: receiving, by a processing core, a synchronization signal; determining, by the processing core, according to the synchronization signal, a first storage area used by a self-task of the processing core and a second storage area used by a non-self-task of the processing core; wherein the first storage area differs from the second storage area; accessing the first storage area to execute the self-task and accessing the second storage area to execute the non-self-task by the processing core. Through the above method, the storage areas corresponding to different tasks of the processing core are separated, which solves the technical problems of complex data consistency processing mechanism and low processing efficiency caused by reading from and writing into the same storage area in the existing technology.

A memory system is provided to include a memory device including a plurality of memory blocks and a controller for dynamically changing a size of a write buffer based on whether a current workload is a sequential workload or a mixed workload. The controller includes a workload detecting unit suitable for changing current workload from the sequential workload to the mixed workload based on a read count, or from the mixed workload to the sequential workload based on a write count and a write buffer managing unit suitable for reducing the size of the write buffer when the current workload is changed to the mixed workload.

A method comprises receiving an input tensor for convolution with a kernel, dividing the input tensor into one or more tiles with each tile having a size equal to the kernel, flattening the values in the one or more tiles into vectors to generate the flattened input stream.

A desktop agent configured to execute on a computer includes a web-application interface and an agent communication port. The web-application interface receives an application launch request for an emergency service application from a web-based application executing in a browser. The emergency service application has a plurality of application communication ports. The agent communication port transmits a launch message to a selected port of the plurality of application communication ports, the selected port selected based on the application launch request. The agent communication port receives, from the selected port, information collected by the emergency service application responsive to the launch message. The desktop agent is configured to transmit the information collected by the emergency service application to a cloud-based computer aided dispatch system.

A system includes a memory device; a volatile memory comprising buffers; and a processing device to perform operations comprising: accessing a read command having a first command tag, the first command tag comprising a first logical transfer unit (LTU) value and a first buffer address for a first buffer, the first LTU value being mapped from a zone of a plurality of sequential logical block address (LBA) values to a first physical address, of the memory device, at which is stored first data; and generating a set of command tags that are to cause second data to be retrieved from the memory device and stored in a set of the buffers, wherein the set of command tags comprises at least a second command tag associated with a second physical address that sequentially follows the first physical address.

An apparatus, system, and method for assigning a cache structure to a catalog. The apparatus includes an identification module configured to identify a catalog for sharing in association with a coupling facility. The coupling facility includes a plurality of cache structures for catalogs of a cluster computing system. The coupling facility is configured to facilitate data sharing among a plurality of host systems of the cluster computing system. The apparatus includes a selection module configured to select a cache structure of the plurality of cache structures for the catalog based on one or more usage status indicators according to an assignment policy. The apparatus includes a storage module configured to store catalog information of the catalog in the cache structure in response to the selection module selecting the cache structure.