In one embodiment, a computer server system includes a memory to store data across memory locations, multiple processing cores including respective local caches in which to cache cache-lines read from the memory, an interconnect to manage read and write operations of the memory and local caches, maintain local cache location data of the cached cache-lines according to respective ones of the memory locations from which the cached cache-lines were read from the memory, receive a write request for a data element to be written to one of the memory locations, find a local cache location in which to write the data element responsively to the local cache location data and the memory location of the write request, and send an update request to a first processing core to update a respective first local cache with the data element responsively to the found local cache location.

In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple addresses of a volatile memory medium VMM of an information handling system (IHS); for each IHS initialization executable/OS executable pair of multiple IHS initialization executable/OS executable pairs: retrieve, from a first non-volatile memory medium (NVMM), an IHS initialization executable of the IHS initialization executable/OS executable pair; copy, by the IHS initialization executable, an OS executable of the IHS initialization executable/OS executable pair from the first NVMM to the VMM; call, by the IHS initialization executable, the subroutine; store, by the subroutine, an address associated with the OS executable via a data structure stored by the VMM; and copy, by a first OS executable, the OS executable from the VMM to a second NVMM based at least on the address associated with the OS executable.

A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

A display method for use in multi-operating systems includes: in a host operating system, allocating a native window to each guest operating system; in the guest operating system, requesting a physical continuous memory (PCM) sub-region corresponding to a window from the host operating system when the window is newly created; in the host operating system, allocating the PCM sub-region to the guest operating system; in the guest operating system, storing rendered data to the PCM sub-region when the newly created window is rendered; and in the host operating system, rendering the native window corresponding to the guest operating system based on the data in the PCM sub-region when a display request from the guest operating system is monitored, and in the host operating system, displaying the native window.

Methods and systems are provided for processing a stream of incoming messages sent from a specific input message source and validating each incoming message of that stream before sending them to a specific target system.

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

A method comprises receiving a kernel used to convolve with an input tensor. For a first dimension of the kernel, a square block of values for each single dimensional vector of the kernel that includes all rotations of that single dimensional vector is generated. For each additional dimension of the kernel, group blocks of an immediately preceding dimension into sets of blocks, each set of blocks including blocks of the immediately preceding dimension that are aligned along a vector that is parallel to the axis of the dimension; and generate, for the additional dimension, one or more blocks of values, each block including all rotations of blocks within each of the sets of blocks of the immediately preceding dimension. The block of values corresponding to the last dimension in the additional dimensions of the kernel is output as the expanded kernel.

An apparatus includes a processor to: based on data dependencies specified in a job flow definition, identify first and second tasks of the corresponding job flow to be performed sequentially, wherein the first task outputs a data object used as an input to the second; store, within a task queue, at least one message conveying at least an identifier of the first task, and an indication that the data object is to be exchanged through a shared memory space; within a task container, in response to storage of the at least one message within the task queue, sequentially execute first and second task routines to sequentially perform the first and second tasks, respectively, and instantiate the shared memory space to be accessible to the first and second task routines during their executions; and upon completion of the job flow, transmit an indication of completion to another device via a network.

A mechanism is described for facilitating sharing of data and compression expansion of models at autonomous machines. A method of embodiments, as described herein, includes detecting a first processor processing information relating to a neural network at a first computing device, where the first processor comprises a first graphics processor and the first computing device comprises a first autonomous machine. The method further includes facilitating the first processor to store one or more portions of the information in a library at a database, where the one or more portions are accessible to a second processor of a computing device.

The disclosure can provide a method and an apparatus for querying application programming interfaces of a webpage, an electronic device, and a storage medium. The method includes: receiving, from a client, a request for querying the interfaces of the webpage, and determining a to-be-analyzed webpage corresponding to the request for querying the interfaces of the webpage;

searching for historical request events of the to-be-analyzed webpage; determining interface addresses invoked when performing the historical request events, and determining invoked interfaces of the to-be-analyzed webpage based on the interface addresses; and generating an interface list based on interface identifiers of the invoked interfaces, and feeding the interface list back to the client.