A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

An image signal processor includes a line interleaving controller and an image signal processor core. The line interleaving controller receives a plurality of image data lines included in an image frame, generates one or more virtual data lines corresponding to the image frame, and outputs the plurality of image data lines and the virtual data lines sequentially line by line. The image signal processor core includes at least one pipeline circuit. The pipe line circuit includes a plurality of processing modules serially connected to sequentially process data lines received from the line interleaving controller. The line interleaving controller processes one or more end image data lines included in an end portion of the image frame based on the virtual data lines. Interference or collision between channels is reduced or prevented by processing the end image data lines in synchronization with the virtual data lines.

Systems and methods for facilitating interactions with remote memory are disclosed. An observing task can execute in a first environment allocated to a first memory space, and a second memory space can be remote from the observing task. An interposition system proxy can invoke at least one function implemented using an ad hoc polymorphic programming language feature to facilitate requests from the observing task to the second memory space. This can include traversing a data structure for at least one target object, resolving an address in the second memory space based on the traversal, and at least one of reading data from and writing data to the resolved address in the second memory space.

Disclosed are mechanisms for sharing managed content through external systems. A sharing module publishes content in a share and metadata associated therewith to an external system. The share represents a folder or directory in a repository managed by an information system such as an enterprise content management system. The publication is made possible through application programming interface (API) calls handled by a first sharing module API, a repository API, a second sharing module API, and an external system API. These APIs together provide a one-to-one mapping of communications protocols used by the managed repository and the external system. The share in the managed repository and the share published to the external system are synced and any conflict between the two is detected and resolved. The shared content can be repatriated back to the managed repository and the shared version deleted from the external system.

Technologies for generating triggered conditional events operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command message associated with a triggered operation that has been fired, process the received operation execution command message to extract and store argument information from the received operation execution command, and increment an event counter associated with the fired triggered operation. The HFI is further configured to perform a triggered compare-and-generate event (TCAGE) operation as a function of the extracted argument information, determine whether to generate a triggering event, generate the triggering event as a function of the performed TCAGE operation, insert the generated triggered event into a triggered operation queue, and update the value of the event counter. Other embodiments are described herein.

A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

In certain embodiments, a method includes starting an application as a first process within a user space of an operating system. The application instantiates a data storage system associated with the operating system. The method also includes starting a block device service as a second process within the user space of the operating system, the block device service being configured to manage a persistent storage device of the computing device. In addition, the method includes receiving, by a kernel of the operating system, a system call request from the application to communicate with the block device service, the system call request is generated by the application using the data storage system and comprises an access request to access the persistent storage device. The method further includes providing the application, in response to the system call request, access to the block device service through the IPC channel.

Method, apparatus and product for automatically introducing register dependency into tests. A test template represents an abstract test scenario to be utilized for testing a target processor. The abstract test scenario requires that a value be assigned to a register. A test that implements the abstract test scenario is generated. The test is a set of instructions that are executable by the target processor. The generation of the test comprises: determining a memory address to retain the value in a memory that is accessible to the target processor; and adding to the test an instruction to load to the register the value from the memory address, whereby adding a register dependency to the test that is not required by the abstract test scenario. The test can be executed on the target processor or simulation thereof.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.