To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

In embodiments of the present disclosure, there is provided a solution for establishing a socket connection in a user space. After receiving a request for establishing a socket connection from a first application, the monitor sends the connection request to a second application, wherein the first application and the second application run on the same computing device. Then, the monitor coordinates establishing, in user space of the operating system, a peer-to-peer socket connection between the first application and the second application. By establishing a socket connection in the user space of the operating system, embodiments of the present disclosure can achieve a user space socket connection between different applications within a single computing device, thereby improving the performance of the operating system. In addition, embodiments of the present disclosure use the monitor (or controller) to coordinate inter-application connection establishment and resource allocation, thereby ensuring security of the operating system.

Aspects of the current subject matter are directed to an approach in which a parallel load operation of file ID mapping containers is accomplished at start and/or restart of a database system. Parallel load operation of file ID mapping and/or large binary object (LOB) file ID mapping is done among a plurality of scanning engines into a plurality of data buffers that are associated with each of the plurality of scanning engines. Each scanning engine operates on a certain path of a page chain of a page structure including the mapping, causing the page chain to be split among scanning engines to process maps. Contents of the data buffers are pushed to mapping engines via a queue. The mapping engines load the file ID mapping and the LOB file ID mapping into maps for in-system access.

Methods and systems for memory resource allocation are disclosed. In an embodiment, a method for memory resource allocation involves reading a pool-specific configuration record from an array of memory mapped pool-specific configuration records according to a memory resource allocation request that is held in an address register of a memory mapped register interface, performing a memory resource allocation operation to service the memory resource allocation request, wherein performing the memory resource allocation operation involves interacting with a resource list according to a pointer in the pool-specific configuration record, advancing the pointer after the interaction, and updating the pointer in the pool-specific configuration record with the advanced pointer.

Systems and methods are provided for implementing an authentication key-based DLL service. For example, the system can expose a list of functionalities and request format, and a byte string denotes a functionality corresponding to the API. Output is received by the user after loading a DLL library maintained by a DLL provider. The system can generate a key corresponding to the functionality and transmit the key to the user. The invocation of the functionality can be performed using the keys. The shared memory space may be used for inputs from the user and outputs of the DLL. The system can perform an action based on the authentication of the keys. During any functionality advancement, the system can notify the user to unload and reload the new DLL in order to make use of the advancements.

A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.

An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and pref etch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of pref etch requests in dependence on reception of the trigger.

Systems and methods for creating a new entry in a hierarchical state data structure with object entries is disclosed. The method includes allocating a shared memory buffer for a new entry in a shared memory. A request to create the new entry for a child object in a hierarchical state data structure in the shared memory is received. The new entry is to span at least one shared memory buffer uniquely identifiable in a location of the shared memory. The child object is a logical representation of a state of a system. In response to a request for an allocation of a shared memory buffer within a region of the shared memory for the new entry, a location identifier corresponding to a location of a parent entry holding a parent object to the child object in the hierarchical state data structure of an allocated region is received. The child object is created in the shared memory buffer for the new entry, and the new entry is available for concurrent access by one or more readers of the shared memory.

There is provided a method for debugging errors in a shared memory. The method comprises executing instrumented machine code of a plurality of processes to generate a recorded execution of each of the plurality of processes for deterministic replay of the recorded execution. The method further comprises logging accesses to the shared memory by each of the plurality of processes in a shared memory log for debugging errors in the shared memory by analysing the recorded executions and the shared memory log. The shared memory log is accessible by each of the plurality of processes.

Based on a predetermined number of available processor sockets, a plurality of candidate matrix decompositions are identified, which correspond to a multiplication of matrices. Based on a first comparative relationship of a variation of first sizes of the plurality of candidate matrix decompositions along a first dimension and a second comparative relationship of a variation of second sizes of the plurality of candidate matrix decomposition sizes along a second dimension, a given candidate matrix decomposition is selected. Processing of the multiplication among the processor sockets is distributed based on the given candidate matrix decomposition.