G06F9/544

Message transmission method and apparatus, device and medium

The present application provides a message transmission method and apparatus, a device and a medium. The method includes: determining and outputting, by an issuing task, a data message, storing the data message in a preset storage space, and sending an issuing notification message; and reading, by a subscription task, the data message from the preset storage space according to the issuing notification message. With embodiments of the present disclosure, transmission efficiency of the data message between the issuing task and the subscription task may be improved, and source occupancy may be reduced.

Optimization of application level parallelism
11366672 · 2022-06-21 · ·

A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources. The operations may include determining and simulating a plurality of application execution paths on a computational platform for generating a report including an analysis of the application algorithm.

Method for generating and processing extended instruction and apparatus using the method

A method for generating and processing extended instructions and an apparatus using the method are provided. The method includes: transmitting, by a first device, a request packet according to an extended instruction that is generated based on a Gen-Z interface standard to a second device; and receiving, by the first device, a response packet including a result of performing the request packet from the second device. The extended instruction is generated based on a vendor-defined instruction set of the Gen-Z interface.

Address mapping between shared memory modules and cache sets
11366752 · 2022-06-21 · ·

A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.

Data linkage system and API platform
11366706 · 2022-06-21 · ·

A data linkage system and an API platform are capable of behaving according to a load of processing executed in response to a request for provision of an API. The data linkage system includes the API platform that provides the API for acquiring data, which is based on data collected by a data collection system and stored in a data storage system for storing data held by an information system, from the data storage system. The API platform determining whether the number of the data that has not been subjected to processing to acquire the data from the data storage system in response to a request for provision of the API satisfies a specific condition, and changing capacity of the processing according to a result of the determination.

Debugging shared memory errors

There is provided a method for debugging errors in a shared memory. The method comprises executing instrumented machine code of a plurality of processes to generate a recorded execution of each of the plurality of processes for deterministic replay of the recorded execution. The method further comprises logging accesses to the shared memory by each of the plurality of processes in a shared memory log for debugging errors in the shared memory by analysing the recorded executions and the shared memory log. The shared memory log is accessible by each of the plurality of processes.

SEAMLESS AUDIO TRANSFER IN A MULTI-PROCESSOR AUDIO SYSTEM

A processing unit for an audio system of a vehicle comprises a first processing node, a second processing node and a program memory. The program memory may be overwritten by the first processing node and by the second processing node. After the processing unit has started up the first processing node may compute and write to the program memory an audio output. The processing unit may also perform a handover of the computing of the audio output from the first processing node to the second processing node when the first processing node has overwritten the program memory up to a predefined point and when the second processing node is operational. The second processing node is designed to compute the audio output after the handover, and to write this audio output to the program memory.

LIGHTWEIGHT ENCRYPTION
20220188426 · 2022-06-16 ·

Briefly, an encryption/decryption algorithm providing for consistent encryption entropy and encryption/decryption performance that is independent of the type of input data.

PROVIDING SUPPLEMENTAL INFORMATION TO A GUEST OPERATING SYSTEM BY A HYPERVISOR
20220188136 · 2022-06-16 ·

Providing supplemental information to a guest operating system by a hypervisor is disclosed. A hypervisor executing on a host computing device initiates a virtual machine comprising a guest kernel. The hypervisor determines an address of a shared memory area that is accessible by the guest kernel and accessible by the hypervisor. The hypervisor determines that an event has occurred for which supplemental information exists, the event corresponding to a particular event code of a plurality of different event codes. The hypervisor determines a location in the shared memory area that corresponds to the particular event code. The hypervisor inserts the supplemental information at the location in the shared memory area. The hypervisor causes an interrupt of the guest kernel.

HARDWARE-BASED PROTECTION OF VIRTUAL FUNCTION RESOURCES
20220188135 · 2022-06-16 ·

Virtual functions are implemented using a plurality of resources and physical function circuitry that executes a virtual function using information stored in the plurality of resources. A processing unit executes a host driver that selectively enables access to the plurality of resources by the virtual function based on an operational state of the processing unit. In some cases, a state machine that determines a state of the virtual function and the host driver that enables access to the plurality of resources by the virtual function based on the state of the virtual function executing on the processing unit. The subsets of the plurality of resources are used to implement a frame buffer, one or more context registers, a doorbell, and one or more mailbox registers.