An automation application is described herein. The automation application executes on a computing device and accesses a macro for a target application. The macro has been generated based upon a sequence of inputs from a user received by the target application that causes the target application to perform an action, screen states of the target application as the target application receives the sequence of inputs from the user, operating system processes that are performed by an operating system as the target application receive the sequence of inputs from the user, and evidence events representing information obtained from the operating system processes. The automation application executes the macro, wherein executing the macro causes the automation application to mimic the sequence of inputs to the target application, thereby causing the target application to perform the action.

Systems and methods are described for processing ingested data using an online machine learning algorithm as the data is being ingested. For example, the online machine learning algorithm can be an adaptive thresholding algorithm used to identify outliers in a moving window of data. As another example, the online machine learning algorithm can be a sequential outlier detector that detects anomalous sequences of logs or events. As another example, the online machine learning algorithm can be a sentiment analyzer that determines whether text has a positive, negative, or neutral sentiment. As another example, the online machine learning algorithm can be a drift detector that detects whether ingested data marks the start of a change in the distribution of a time-series.

Techniques for computing and storing object identity hash values are disclosed. In some embodiments, a runtime system generates a value, such as a nonce, that is unique to a particular allocation region within memory. The runtime system may mix the value with one or more seed values that are associated with one or more respective objects stored in the allocation region. The runtime system may obtain object identifiers for the respective objects by applying a hash function to the result of mixing the seed value with at least the value associated with the allocation region. Conditioning operations may also be applied before, during or after the mixing operations to make the values appear more random. The nonce value may be changed from time to time, such as when memory is recycled in the allocation region, to reduce the risk of hash collisions.

A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator. The data transfer instructions may be conveyed in a plurality of sequential data transfer phases that correspond to the transfer instruction subsets.

In an embodiment a method includes determining, by an electronic device, whether a second shared library having the same file data as a first shared library of a first APP exists in the electronic device, when the second shared library exists in the electronic device, storing a correspondence between a first index node (inode) and a file name of the first shared library, deleting the file data of the first shared library from the electronic device, and allocating the first inode to the second shared library, wherein the first inode indicates a first storage area used to store file data of the second shared library; and when the electronic device runs the first APP to invoke the first shared library, searching for the first inode corresponding to the file name of the first shared library and reading the file data of the second shared library stored in the storage area indicated by the first inode.

Some embodiments provide a method for performing radio access network (RAN) functions in a cloud at a medium access control (MAC) scheduler application that executes on a machine deployed on a host computer in the cloud. The method receives data, via a RAN intelligent controller (RIC), from a first RAN component. The method uses the received data to generate a MAC scheduling output. The method provides the MAC scheduling output to a second RAN component via the RIC.

Examples described herein include systems and methods for brokerless reliable totally ordered many-to-many inter-process communication on a single node. A messaging protocol is provided that utilizes shared memory for one of the control plane and data plane, and multicast for the other plane. Readers and writers can store either control messages or message data in the shared memory, including in a ring buffer. Write access to portions of the shared memory can be controlled by a robust futex, which includes a locking mechanism that is crash recoverable. In general, the writers and readers can control the pace of communications and the crash of any process does not crash the overall messaging on the node.

To synchronize operations of a computing system, a new type of synchronization barrier is disclosed. In one embodiment, the disclosed synchronization barrier provides for certain synchronization mechanisms such as, for example, “Arrive” and “Wait” to be split to allow for greater flexibility and efficiency in coordinating synchronization. In another embodiment, the disclosed synchronization barrier allows for hardware components such as, for example, dedicated copy or direct-memory-access (DMA) engines to be synchronized with software-based threads.

A data processing apparatus comprises one or more memories storing instructions and one or more processors that, upon execution of the instructions, are configured to sequentially perform processing of data by a plurality of hierarchically connected processing nodes, store, in the one or more memories, processing results of the plurality of respective processing nodes, and processing statuses of and parameters for the plurality of respective processing nodes, the parameters being used determine a processing node to perform the processing, cyclically specify processing nodes, from among the plurality of processing nodes, to perform the processing in an order based on hierarchy, determine whether the processing by a specified processing node is performable based on the stored processing statuses, and determine a processing node to perform the processing based on a result of determination and the stored parameter for the specified processing node.