Apparatuses, systems, and techniques to perform one or more APIs. In at least one embodiment, a processor is to perform an API to deselect storage selected to be used to transfer information between a plurality of fifth generation new radio (5G-NR) computing resources.

Apparatuses, systems, and techniques to perform one or more APIs. In at least one embodiment, a processor is to perform an API to select storage to be used to transfer information between a plurality of fifth generation new radio (5G-NR) computing using different transport protocols.

Apparatuses, systems, and techniques to perform one or more APIs. In at least one embodiment, a processor is to perform an API to prevent deselection of storage to be used to transfer information between a plurality of fifth generation new radio (5G-NR) computing using different transport protocols.

Apparatuses, systems, and techniques to perform one or more APIs. In at least one embodiment, a processor is to perform an API to obtain data from storage selected to be used to transfer information between a plurality of fifth generation new radio (5G-NR) computing resources.

A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

A system, methods, and devices for solid state device (SSD) simulation are provided. An application is executed at a virtual machine. Buffer pointers for application data of the executed application are sent from the virtual machine to a shared memory. The application data is copied from the virtual machine to data buffer pages of the shared memory. The buffer pointers are sent from the shared memory to an SSD simulator. The buffer pointers and corresponding references to the application data at the shared memory are stored in pages of a cache of the SSD simulator.

A resource management device includes a processor configured to update registered process information indicating priority of a process being executed and an area in a shared resource used by the process, at every start or end of execution of one of processes using the shared resource, determine, when a first process being executed rewrites data stored in the shared resource, whether a second process using an area in the shared resource used by the first process exists, by referring to the registered process information, interrupt the first process until termination of the second process when the second process having higher priority than the first process exists, and interrupt the second process until termination of the first process when the second process having lower priority than the first process exists.

Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

A memory system is provided to include a first virtual function controller in communication with a first virtual machine of a host and configured to receive, from the first virtual machine, a command for accessing a namespace and provide, to the first virtual machine, a response to the command; a second virtual function controller in communication with a second virtual machine of the host and configured to be coupled to the namespace and receive the command from the first virtual function controller based on status information of the first virtual function controller and the second virtual function controller; a buffer memory configured to provide an area for data corresponding to the command; and a memory controller configured to access the namespace based on the command and provide the buffer memory with the data.

An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.