Devices and techniques for triggering early termination of cooperating processes in a processor are described herein. A system includes multiple memory-compute nodes, wherein a memory-compute node comprises: event manager circuitry configured to establish a broadcast channel to receive event messages; and thread manager circuitry configured to organize a plurality of threads to perform portions of a cooperative task, wherein the plurality of threads each monitor the broadcast channel to receive event messages on the broadcast channel, and wherein upon achieving a threshold operation, the thread manager circuitry is to use the event manager circuitry to broadcast, on the broadcast channel, an event message indicating that the cooperative task is complete, causing other threads, in response to receiving the event message, to terminate execution of their respective portions of the cooperative task.

The “free world replication protocol” makes use of client computing resources, wherein the clients are not part of the replicated key-value store, but instead reside in the “free world” outside of the dedicated resources of the nodes of the replicated key-value store. In the free world replication protocol, only a single “write” client is authorized to modify the key-value store at any time but any number of clients may be authorized to read data from the key-value store. The write client sends its transactions to multiple nodes in the replicated key-value store. As a result, the latency between the transaction being sent from the client and the transaction being received by the multiple nodes is reduced. A consensus protocol, driven by a master node, is used to periodically ensure consistency, but the data transactions themselves do not make use of a master node.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

In a computer-implemented method for performing alert notification on streaming textual data, streaming textual data is received. A plurality of copies of the streaming textual data is generated, wherein a first copy of the streaming textual data is transmitted to an ingestion service for persistent storage at a data plane and a second copy of the streaming textual data is transmitted to an alert evaluation service for performing alert evaluation on the streaming textual data, such that the ingestion service and the alert evaluation service are performed independently. The streaming textual data is evaluated by the alert evaluation service to detect an alert. Responsive to detecting an alert at the alert evaluation service, a notification of the alert is generated.

Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.

A computer system receives, in a first messaging conversation by a first messaging application of a plurality of applications, information identifying a first shared content item. In response to receiving the information identifying the first shared content item, in accordance with a determination that the first shared content item is of a first type, the computer system automatically makes the first shared content item available within a first application of the plurality of applications, the first application is associated with content of the first type. In accordance with a determination that the first shared content item is of a second type, the computer system automatically makes the first shared content item available within a second application of the plurality of applications, wherein the second application is associated with content of the second type.

A message-based processor has at least one processor cluster. The processor cluster includes a plurality of processor cluster elements. Each processor cluster element has an operational mode indicator that indicates an operational mode of the processor cluster element, such as a transmission disabling operational mode and a transmission enabling operational mode. In some examples, the message-based processor sets a particular processor cluster element of the plurality of processor cluster elements to the transmission disabling operational mode and transmits, with a delay, a re-enable control message to the particular processor cluster element to reassume the transmission enabling operational mode.

Systems, apparatuses, and methods for generating network messages on a parallel processor are disclosed. A system includes at least a parallel processor, a general purpose processor, and a network interface unit. The parallel processor includes at least a plurality of compute units, a command processor, and a cache. A thread within a kernel executing on a compute unit of the parallel processor generates a network message and stores the network message and a corresponding indication in the cache. In response to detecting the indication of the network message in the cache, the command processor processes and conveys the network message to the network interface unit without involving the general purpose processor.

Methods and systems are provided for processing a stream of incoming messages sent from a specific input message source and validating each incoming message of that stream before sending them to a specific target system.