A method for constructing a persistent memory index in a non-uniform memory access architecture includes: maintaining partial persistent views in a persistent memory and maintaining a global volatile view in a DRAM; an underlying persistent memory index processing a request in a foreground thread when cold data is accessed; when hot data is accessed, reading a key-value pair for a piece of hot data in the global volatile view in response to a query operation carried in the request, and in response to an insert/update/delete operation carried in the request, updating a local partial persistent view and the global volatile view; and in response to a hotspot migration, a background thread generating new partial persistent views and a new global volatile view, and recycling the partial persistent views and the global volatile view for old hot data into the underlying persistent memory index.

Systems and methods for predicting whether a nonvolatile memory block is likely capable of being securely erased to be eligible for composing into another composable infrastructure are described. A management module receives a secure-erase command to erase at least one nonvolatile memory block, determines health parameters of the nonvolatile memory block, calculates a failure index based on the health parameters, and, based on the failure index, either securely erases the block of memory or retires the nonvolatile memory block.

An information processing apparatus includes a processor configured to acquire first information that indicates a correspondence relationship between a virtual identifier of a memory device and a first identifier of a slot to which the memory device is attached, acquire second information that indicates a correspondence relationship between a second identifier of a slot to which the memory device is attached and a state of the memory device, generate correspondence information that indicates a correspondence relationship among the virtual identifier, the first identifier, and the second identifier based on the first information and the second information, acquire, during an operation of the distributed storage, third information that indicates correspondence relationship between the virtual identifier and the first identifier and fourth information that indicates correspondence relationship between the second identifier and the state of the memory device, and update the correspondence information based on the third information and the fourth information.

Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

A position-measuring device includes a graduation carrier having a measuring graduation, position measurement electronics, a data memory and a power supply. The data memory includes a first memory which is a volatile memory for storing additional data, a second memory which is a writable non-volatile memory, and a memory controller for controlling transfer and storage of additional data from the first into the second memory. The power supply includes an input stage, a first output stage for the position measurement electronics, a second output stage for the data memory, and a voltage monitor which will turn off the first output stage of the power supply in response to a drop below a minimum value and signal the drop to the memory controller by a backup signal. In response to the backup signal, the memory controller will transfer additional data from the first memory into the second memory.

In some examples, a system records, in a data structure stored in a non-volatile storage, information of memory errors in respective segments of a memory. The system determines whether memory errors of a subset of the segments satisfy a criterion, and in response to determining that the memory errors of the subset of the segments satisfy the criterion, the system groups the memory errors of the subset into a partition having a size greater than a size of a segment. The system records, in the data structure, information of memory errors in the partition, and in response to a restart of the system, retrieves the data structure from the non-volatile storage for use in an operation that addresses memory errors in the system.

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.