A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.

Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

An object of the invention is to improve communication quality in a power storage management system.

The above-mentioned problem may be solved by the following one solution. When a communication error where transmission, reception, or both transmission and reception of a signal is not allowed occurs between one or a plurality of a plurality of information acquisition devices that acquires states of a plurality of power storage cells and an information collection device that communicates with the plurality of information acquisition devices in a time-division manner, and collects information related to the states of the plurality of power storage cells acquired by the plurality of respective information acquisition devices, a process for resolving a communication error is executed by putting all the plurality of information acquisition devices in a state in which communication with the information collection device is allowed at all times. Here, the plurality of information acquisition devices is in a state in which communication with the information collection device is allowed in a first period in which the plurality of information acquisition devices communicates with the information collection device, and is in a state in which the state, in which communication with the information collection device is allowed, is canceled in a second period in which other information acquisition devices communicate with the information collection device in a relation of n to 1 (n is a positive natural number indicating the number of communication channels of the information collection device).

A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.

An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

Systems and methods are described for optimizing logging of decision outcomes in distributed transaction protocols. An example method may comprise: executing, by a processing device, a transaction manager to coordinate a distributed transaction for a plurality of participants; transmitting, by the processing device via the transaction manager, prepare messages to the plurality of participants; serializing a transaction log record of the distributed transaction in parallel with the transmitting of the prepare messages; speculatively writing the serialized transaction log record in persistent memory while the transaction manager performs the serializing of the transaction log record; and updating a speculative indicator associated with the distributed transaction to indicate validity of the transaction log record.

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

In example implementations, an apparatus is provided. The apparatus includes a processor and a non-transitory computer readable medium storing instructions. The instructions are executed by the processor to monitor user interaction with the apparatus, detect an abnormal user interaction with the apparatus, and activate a digital assistant in response to the abnormal user interaction that is detected. The digital assistant can collect user information related to the abnormal user interaction.

A failure of communication between a first device and a second device is managed. A failure of communication between the first device and the second device is detected at a third device intermediate. The first data is transmitted from the third device to the first device. The first data indicates that the second device is unusable by the first device.