Disclosed embodiments include an electronic device having a write-once memory (WOM) and a memory controller. The memory controller includes a host interface receiving a data word including first and second symbols, each having at least two bits, a WOM controller that encodes the first and second symbols and outputs a WOM-encoded word including first and second WOM codes corresponding to the first and second symbols, respectively, an error correction code (ECC) controller that encodes the WOM-encoded word and outputs an ECC-encoded word including the first and second WOM codes and a first set of ECC bits corresponding to a first write operation, and a memory device interface that writes the ECC-encoded word the WOM device in the first write operation. Each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value.

A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory. When the data storage device is initiated, or when the data size read by a host is greater than a threshold value, the controller inspects the status of the data stored by the physical pages of the memory.

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.

System and methods are disclosed including a plurality of memory devices and a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising: receiving, from a host system, encrypted write data appended with error-checking data; determining whether the encrypted write data contains an error based on the error-checking data; and responsive to determining that the encrypted write data contains an error, notifying the host system that the encrypted write data contains an error.

According to one embodiment, a memory system is connectable to a host including a first volatile memory and includes a non-volatile memory and a controller. The controller may use a first area of the first volatile memory as a temporary storage memory of data stored in the non-volatile memory and controls the non-volatile memory. The controller generates a first parity by using first data stored in the non-volatile memory and a key value to store the first data and the generated first parity in the first area. In the case of reading the first data stored in the first area, the controller reads the first data and the first parity to verify the read first data using the read first parity and the key value.

One example method includes receiving an IO request that specifies an operation to be performed concerning a data block, determining if a policy exists for a device that made the IO request, when a policy is determined to exist for the device, comparing the IO request to the policy, recording the IO request, and passing the IO request to a disk driver regardless of whether the IO request is determined to violate the policy or not.

The disclosure herein describes elastically managing the execution of workers of multi-worker workloads on accelerator devices. A first worker of a workload is executed on an accelerator device during a first time interval. A first context switch point is identified when the first worker is in a first worker state. At the identified context switch point, a first memory state of the first worker is stored in a host memory and the accelerator device is configured to a second memory state of the second worker. The second worker is executed during a second time interval and a second context switch point is identified at the end of the second time interval when the second worker is in a state that is equivalent to the first worker state. During the intervals, collective communication operations between the workers are accumulated and, at the second context switch point, the accumulated operations are performed.

Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.

First and second data are identified, such that the second data is based on a modification operation performed on the first data. First error-checking data comprising a Cyclic Redundancy Check (CRC) value of the first data is identified. Incremental error-checking data is generated based on a difference between the first data and the second data. Updated first error-checking data is generated based on a combination of the first error-checking data and the incremental error-checking data. The updated first error-checking data is compared to second error-checking data generated from a CRC value of the second data to determine whether the second data contains an error.