G06F11/1008

Method and apparatus for failure recovery of storage device

Techniques perform failure recovery of a storage device. The techniques involve: determining, based on failure data indicating at least one failed disk, whether the at least one failed disk comprises a system disk associated with an extent pool of the storage device, the extent pool being built based on system disks and user disks; in response to determining that the at least one failed disk comprises a system disk, rebuilding the user data of the system disk to one or more further disks associated with the extent pool; and in response to the system disk being replaced with an updated system disk, restoring the rebuilt user data from the one or more further disks to the updated system disk, an association of the system disk with the extent pool being maintained until the system disk is replaced by the updated system disk.

Read latency improvement method and memory system thereof
10943634 · 2021-03-09 · ·

A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.

APPARATUS FOR CALIBRATING SENSING OF MEMORY CELL DATA STATES

Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.

Memory control method, memory storage device and memory control circuit unit

A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

The present disclosure relates to a structure including a memory built-in self test (MBIST) circuit which is configured to repair a multi-cell failure for a plurality of patterns in a single wordline of a sliding window of a memory.

CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FOR BOTH READ AND WRITE DATA TRANSMITTED VIA BIDIRECTIONAL DATA LINK
20210081269 · 2021-03-18 ·

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Memory buffer with data scrambling and error correction
11854658 · 2023-12-26 · ·

A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Intelligent post-packaging repair
10909011 · 2021-02-02 · ·

Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.

Data storage device and data retrieval method
11061764 · 2021-07-13 · ·

A data storage device includes a flash memory and a controller. The flash memory includes a plurality of dies, and each of the dies includes a first memory plane and a second memory plane, wherein each of the first memory plane and the second memory plane includes a plurality of physical pages. The controller retrieves data of a first physical page of the first memory plane and data of a second physical page of the second memory plane in response to a read command which is arranged to read a target page.

METHOD AND SYSTEM FOR ENHANCING THROUGHPUT OF BIG DATA ANALYSIS IN A NAND-BASED READ SOURCE STORAGE
20210026731 · 2021-01-28 · ·

One embodiment facilitates data access in a storage device. During operation, the system obtains, by the storage device, a file from an original physical media separate from the storage device, wherein the file comprises compressed data which has been previously encoded based on an error correction code (ECC). The system stores, on a physical media of the storage device, the obtained file as a read-only replica. In response to receiving a request to read the file, the system decodes, by the storage device based on the ECC, the replica to obtain ECC-decoded data, wherein the ECC-decoded data is subsequently decompressed by a computing device associated with the storage device and returned as the requested file.