Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Systems and methods for limiting performance variation in a storage device are described. Storage devices receive work requests to perform one or more operations from other computing devices, such as a host computing device. Completing the work requests may take a response time. In some embodiments, if the response time of executing the work request exceeds a threshold, the storage device may assign additional computing resources to complete the work request.

Techniques described and suggested herein include systems and methods for optimizing performance characteristics by differentiating data storage device types for data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be stored on different types of data storage devices to optimize for various retrieval use cases and implemented environments. Implementing systems may monitor various performance characteristics so as to adaptively account for changes to some or all of the monitored parameters.

Provided is a 5.sup.th generation (5G) or 6.sup.th generation (6G) communication system for supporting higher data rates after 4G communication systems such as long term evolution (LTE). A communication method of a user equipment (UE) includes receiving, from a base station (BS), information about a decoding mode including bit information corresponding to the number of times of perturbation, receiving data from the BS on a Physical Downlink Shared Channel (PDSCH), and decoding the received data based on the information about the decoding mode, wherein the information about the decoding mode may be generated based on service information including at least one of Quality of Service (QoS), a service priority, packet delay performance, packet error probability performance, a requirement, or a data transmission scheme.

Methods and systems for enhanced error recovery are described. A first one or more data blocks to write to a first drive are received by a first drive controller module. A first parity block is calculated by the first drive controller module based on a first data block parity group. The first one or more data blocks are written by the first drive controller module to the first drive. The first parity block is written by the first drive controller module to the first drive.

A system for data storage includes one or more non-volatile memory (NVM) devices, each device including multiple memory blocks, and a processor. The processor is configured to assign the memory blocks into groups, to apply a redundant data storage scheme in each of the groups, to identify a group of the memory blocks including at least one bad block that renders remaining memory blocks in the group orphan blocks, to select a type of data suitable for storage in the orphan blocks, and to store the data of the identified type in the orphan blocks.

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B.sub.0, B.sub.1). A first data state (0) is written to a signal bit (B.sub.i) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Provided is a 5.sup.th generation (5G) or 6.sup.th generation (6G) communication system for supporting higher data rates after 4G communication systems such as long term evolution (LTE). A communication method of a user equipment (UE) includes receiving, from a base station (BS), information about a decoding mode including bit information corresponding to the number of times of perturbation, receiving data from the BS on a Physical Downlink Shared Channel (PDSCH), and decoding the received data based on the information about the decoding mode, wherein the information about the decoding mode may be generated based on service information including at least one of Quality of Service (QoS), a service priority, packet delay performance, packet error probability performance, a requirement, or a data transmission scheme.

A data storage device and method for preventing data loss during an ungraceful shutdown are provided. In one embodiment, a data storage device is provided comprising a volatile memory; a non-volatile memory; and a controller. The controller is configured to detect an ungraceful shutdown; and in response to detecting the ungraceful shutdown: generate a reduced set of parity bits for data stored in the volatile memory, wherein the reduced set of parity bits comprises fewer parity bits than a full set of parity bits used in a graceful shutdown; and store the data and the reduced set of parity bits in the non-volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.